Confusion about segment addressing - ASM x86 ASM 370
This is a discussion on Confusion about segment addressing - ASM x86 ASM 370 ; Hello,
I have a question on the 8088 family of microprocessors. Can someone
kindly explain REAL mode segment ffset addressing with reference to
the following example:
DS contains 0xB000
SI contains 0x8000
The books say DS is SHIFTED LEFT by ...
-
Confusion about segment addressing
Hello,
I have a question on the 8088 family of microprocessors. Can someone
kindly explain REAL mode segment
ffset addressing with reference to
the following example:
DS contains 0xB000
SI contains 0x8000
The books say DS is SHIFTED LEFT by 4 bits - giving
0xB0000 - How? The 'B' bits 1011 will be shifted out leaving
0x0000. How is it left shifted and where is it stored - ALL registers
are only 16 bits - NONE is 20 bits.
How does this 0x B0000
0x 8000
------------------
B8000 ---- Physical Address
This Addition take place? Where is the 20 bit 0x B0000 stored?? How
does this left shift take place, I think it gives 0000 instead of B0000
and if the latter then where will it be stored? all are 16 bit - not
20.This is the first query.
Secondly, where does the addition take place ? In some kind of circuit
? -which outputs directly to the address bus?
I will be grateful if someone can explain these simply, I find it very
confusing. Thanks a Lot,
Krishna
-
Re: Confusion about segment addressing
"Krishna" <spamtrap@crayne.org> writes:
> The books say DS is SHIFTED LEFT by 4 bits - giving
>
> 0xB0000 - How? The 'B' bits 1011 will be shifted out leaving
> 0x0000. How is it left shifted and where is it stored - ALL registers
> are only 16 bits - NONE is 20 bits.
It doesn't use registers, it uses an internal 20 bit latch. This
isn't software any more, this is hardware - "shifting" is as easy as
attaching the wires four places over, and they can add more bits as
needed.
Now, if your *program* wants to compute the physical address, that's a
different problem, which *would* be affected by the 16 bit limitation.
> This Addition take place? Where is the 20 bit 0x B0000 stored??
In a 20 bit hardware latch.
> How does this left shift take place,
The 16 wires are connected to inputs 4..19 of an internal 20 bit
adder.
> I think it gives 0000 instead of B0000
Obviously, it doesn't, since the chip works.
> Secondly, where does the addition take place ? In some kind of
> circuit? -which outputs directly to the address bus?
Yes. There are no "registers" involved at that point, so there's no
16 bit limit.
-
Re: Confusion about segment addressing
Krishna wrote:
> Hello,
>
> I have a question on the 8088 family of microprocessors. Can someone
> kindly explain REAL mode segment
ffset addressing with reference to
> the following example:
>
> DS contains 0xB000
> SI contains 0x8000
>
> The books say DS is SHIFTED LEFT by 4 bits - giving
>
Yes, this description is poor, it has been a poor description from the
beginning. This description implies to most first time readers as a
-register- shift, it is not. It is an attempt to describe simply this:
regarding segm
ffs, the Segment Register holds the upper 16 bits of a
20 bit linear address. The Offset is the lower 16 bits of a 20bit
linear address. To combine both into a physical address, add the two
together _as if_ the segment value is nibble extended.
This physical address is held in an internal register of the cpu
governing the address buss.
> 0xB0000 - How? The 'B' bits 1011 will be shifted out leaving
> 0x0000. How is it left shifted and where is it stored - ALL registers
> are only 16 bits - NONE is 20 bits.
>
> How does this 0x B0000
> 0x 8000
> ------------------
> B8000 ---- Physical Address
>
> This Addition take place? Where is the 20 bit 0x B0000 stored?? How
> does this left shift take place, I think it gives 0000 instead of B0000
> and if the latter then where will it be stored? all are 16 bit - not
> 20.This is the first query.
>
> Secondly, where does the addition take place ? In some kind of circuit
> ? -which outputs directly to the address bus?
>
This physical address is held in an internal register of the cpu
governing the address buss.
Steve
> I will be grateful if someone can explain these simply, I find it very
> confusing. Thanks a Lot,
>
> Krishna
-
Re: Confusion about segment addressing
Thanks ALL of you for responding. The description of "shifting"
"implying" register shifting confused me. I looked up the Latch and
Adder on the internet, thanks to your replies.Thanks once again,
Krishna
spamtrap@crayne.org wrote:
> Krishna wrote:
> > Hello,
> >
> > I have a question on the 8088 family of microprocessors. Can someone
> > kindly explain REAL mode segment
ffset addressing with reference to
> > the following example:
> >
> > DS contains 0xB000
> > SI contains 0x8000
> >
> > The books say DS is SHIFTED LEFT by 4 bits - giving
> >
> Yes, this description is poor, it has been a poor description from the
> beginning. This description implies to most first time readers as a
> -register- shift, it is not. It is an attempt to describe simply this:
> regarding segm
ffs, the Segment Register holds the upper 16 bits of a
> 20 bit linear address. The Offset is the lower 16 bits of a 20bit
> linear address. To combine both into a physical address, add the two
> together _as if_ the segment value is nibble extended.
> This physical address is held in an internal register of the cpu
> governing the address buss.
>
> > 0xB0000 - How? The 'B' bits 1011 will be shifted out leaving
> > 0x0000. How is it left shifted and where is it stored - ALL registers
> > are only 16 bits - NONE is 20 bits.
> >
> > How does this 0x B0000
> > 0x 8000
> > ------------------
> > B8000 ---- Physical Address
> >
> > This Addition take place? Where is the 20 bit 0x B0000 stored?? How
> > does this left shift take place, I think it gives 0000 instead of B0000
> > and if the latter then where will it be stored? all are 16 bit - not
> > 20.This is the first query.
> >
> > Secondly, where does the addition take place ? In some kind of circuit
> > ? -which outputs directly to the address bus?
> >
> This physical address is held in an internal register of the cpu
> governing the address buss.
> Steve
>
> > I will be grateful if someone can explain these simply, I find it very
> > confusing. Thanks a Lot,
> >
> > Krishna
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