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| In article <20080824134656.2f1018d1@thor.crayne.org>, spamtrap@crayne.org says... > On Sun, 24 Aug 2008 20:21:26 +0300 > Phil Carmody <thefatphil_demunged@yahoo.co.uk> wrote: > > > I've known architectures > > where the two halves of the fetch from memory (or should I say > > two fetches from memory) would leave room for a race condition, > > and currently have no reason to believe that x86 would be any > > different. > > In the 8086/8088 days, this was a potential problem, but since the > introduction of cache memory, the designers have provided ways to > synchronize the caches on two or more processors, and all reads, > and most writes, are atomic. Only those instructions which internally > perform a read->update->write cycle can make use of the LOCK prefix, > although there may be assemblers which will silently discard the > prefix when it is used inappropriately. This has been true since at > least the introduction of the 80386. This isn't really true, but it can look that way most of the time. It's all really a question of HOW badly misaligned an item can get before it gets read and/or written in a non-atomic fashion. On a reasonably current machine, if an item crosses a cache line boundary, it won't be read/written atomically. -- Later, Jerry. The universe is a figment of its own imagination. |
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