primitives vs cleverness vs readability

On 11 Aug, 16:11, stephen...@mpeforth.com (Stephen Pelc) wrote:
> On Mon, 11 Aug 2008 06:42:33 -0700 (PDT), jacko <jackokr...@gmail.com>
> wrote:
>
> >On 8 Aug, 13:42, stephen...@mpeforth.com (Stephen Pelc) wrote:
> >Yeah probbly large code pointers used mainly full of some constant in
> >the upper 16 bit.
> >Low level words should generate at most 1 CALL. There is very little
> >reason not to use 16 bit addressing
>
> When we started serious NCC development, we very quickly learned to
> trust measured results over opinion. That's why we developed and
> published a simple set of integer benchmarks
> *http://www.mpeforth.com/arena/benchmrk.fth
> *http://www.mpeforth.com/arena/xbench32.fth
>
> You are welcome to publish your results.

I will if I implement all the required word set or the benchmark, but
a result of 332 LEs for the processor testifies to its compactness.

> >> On silicon stack machines, Chuck Moore certainly doesn't agree
> >> with you. Some Forth-machine FPGA implementations have reached
> >> several hundreds of MIPs, but I'm not free to say more.
>
> >Yes and they probably don't use the lowest speed grade and have
> >pockets bigger than there heads.
>
> If you come to EuroForth 2008 in Vienna, you can talk to people
> who have shipped silicon and used silicon stack machines for real
> applications.

Yes if I developed a hole in my pocket that big maybe I'd go. Your
condicending tone makes me somewhat disinterested, Whats your personal
4 LUT benchmark?

> Stephen
>
> --
> Stephen Pelc, stephen...@mpeforth.com
> MicroProcessor Engineering Ltd - More Real, Less Time
> 133 Hill Lane, Southampton SO15 5AF, England
> tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691
> web:http://www.mpeforth.com- free VFX Forth downloads

Jacko

-- Simon Jackson, BEng. jackokring@gmail.com
K Ring Technologies Semiconductor - Smaller, Less Baggage
NFA
Tel: +44 (0)7967973001 Fax: F**K OFF and use E-mail
web: ttp://nibz.googlecode.com - Free IP Core (BSD (C) Excemption Cash
Licence Available)

On 14 Aug, 11:52, Andrew Haley <andre...@littlepinkcloud.invalid>
wrote:
> Anton Ertl <an...@mips.complang.tuwien.ac.at> wrote:
> > Andrew Haley <andre...@littlepinkcloud.invalid> writes:
> > >Anton Ertl <an...@mips.complang.tuwien.ac.at> wrote:
> > >> Andrew Haley <andre...@littlepinkcloud.invalid> writes:
> > >> >Anton Ertl <an...@mips.complang.tuwien.ac.at> wrote:
> > >> >> Andrew Haley <andre...@littlepinkcloud.invalid> writes:
> > >> >> >There's no reason at all to use 64-bit threading on a 64-bit
> > >> >> >processor.
>
> > >> >> There are a number of reasons:
>
> > >> >> * Nothing at all guarantees that the code is all in the lower 4G
> > >> >> of the address space (and on at least one platform it isn't), and
> > >> >> the gcc maintainers and others have a tendency to break the gcc
> > >> >> behaviour that we rely on;
>
> > >> >Of course, this isn't something gcc maintainers have any control over.
>
> > >> The gcc maintainers do not have any control over gcc behaviour?
>
> > >This isn't gcc behaviour.
> > If gcc introduces crossjumps and pointlessly reorders the basic
> > blocks, that's not gcc behaviour?
>
> What on Earth does reordering basic blocks have to do with any of
> this?
>
> > >> >I don't know who "others" may be!
>
> > >> In the example below, I guess it was the binutils maintainers.
>
> > >Perhaps, but the address at which a program is loaded probably isn't
> > >controlled by the binutils maintainers either.
> > So, you are saying that nobody is responsible for code placement,
>
> I don't know. *Maybe the kernel or libc, maybe both. *This sort of
> thing is usually worked out by negotiation between the teams.
>
> > nobody gives us a guarantee for it, but we should rely on it being
> > in the lower 4G.
>
> This one is guaranteed by the ABI. *The "small" x86_64 model depends
> on it.
>
> > Hmm, OTOH, would thse unknown people be worse than the gcc
> > maintainers? *Probably not.
> > >> Hmm, thinking again about it, with ITC it's necessarily so. *With ITC,
> > >> the addresses you put in the threaded code are not code addresses, but
> > >> code-field addresses, i.e., general dictionary addresses. *If you
> > >> restrict these to 32 bits, you restrict the dictionary to the lower
> > >> 4G. *What kind of 64-bit system would that be?
>
> > >Obviously, that'd be a 64-bit system with code restricted to the lower
> > >4G. *The non-code part of the dictionary could be anywhere. obviously.
> > With the unusual definition of "code" that includes every word header,
> > including those of e.g., constants and CREATEd words.
>
> I don't see why the whole header must be there. *Just the code field,
> surely.

The ROMable fields?

> Andrew.- Hide quoted text -
>
> - Show quoted text -

On Fri, 15 Aug 2008 07:34:53 -0700 (PDT), jacko <jackokring@gmail.com>
wrote:

>Yes if I developed a hole in my pocket that big maybe I'd go. Your
>condicending tone makes me somewhat disinterested, Whats your personal
>4 LUT benchmark?

I did not mean to be condescending. If the objective is to use the
lowest number of FPGA blocks, why? What else will be in the FPGA?

Stephen


--
Stephen Pelc, stephenXXX@mpeforth.com
MicroProcessor Engineering Ltd - More Real, Less Time
133 Hill Lane, Southampton SO15 5AF, England
tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691
web: http://www.mpeforth.com - free VFX Forth downloads

On 18 Aug, 10:08, stephen...@mpeforth.com (Stephen Pelc) wrote:
> On Fri, 15 Aug 2008 07:34:53 -0700 (PDT), jacko <jackokr...@gmail.com>
> wrote:
>
> >Yes if I developed a hole in my pocket that big maybe I'd go. Your
> >condicending tone makes me somewhat disinterested, Whats your personal
> >4 LUT benchmark?
>
> I did not mean to be condescending. If the objective is to use the
> lowest number of FPGA blocks, why? What else will be in the FPGA?
>
> Stephen
>
> --
> Stephen Pelc, stephen...@mpeforth.com
> MicroProcessor Engineering Ltd - More Real, Less Time
> 133 Hill Lane, Southampton SO15 5AF, England
> tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691
> web:http://www.mpeforth.com- free VFX Forth downloads

Well in reality of budget constrants it's a CPLD with 1270 LEs, not a
mega dollar fpga.
http://nibz.googlecode.com processor, and also 2*Phase Ultrasonic DAC
(FREE for nibz site, Not BSD) with DMA sequencer, quite likely a
keyboard of some kind, and maybe even a PIO Mode 4 hard disk
controller. O yes, and some kind of display driver. It will be a tight
fit.

cheers
jacko

Hi

Look at it like this, a plastic cased fpga synth, versus a simpler
CPLD synth with differing tonal character is a quality stainless case,
with ALPS treacle pots. Budget is to do with feel. Electronic
complexity is not the be all and end all.

cheers
jacko

Recessed ALPS treacle pots, "better knobs in than off". ;-)

On Aug 18, 9:04*am, jacko <jackokr...@gmail.com> wrote:
>
> Well in reality of budget constrants it's a CPLD with 1270 LEs, not a
> mega dollar fpga.

Altera's online store lists this CPLD at $22.70 for the cheapest one.
Compare with $12.80 for the cheapest CycloneIII.

Okay, you probably want a secure bitstream. Spartan3A has that covered
with their "Device DNA" trick. Digikey lists the XC3S50A-4TQ144C at
$10.02 and it boots from a standard serial SPI flash. All pricing is
in onesies.

This is getting pretty far off-topic but it does illustrate that
putting Forth in FPGAs is getting much more cost effective these days.
Limited internal memory will favor Forth's shrewd use of resources for
the next 10 years at least.

-Brad

On 18 Aug, 18:18, Brad Eckert <nospaambr...@tinyboot.com> wrote:
> On Aug 18, 9:04*am, jacko <jackokr...@gmail.com> wrote:
>
>
>
> > Well in reality of budget constrants it's a CPLD with 1270 LEs, not a
> > mega dollar fpga.
>
> Altera's online store lists this CPLD at $22.70 for the cheapest one.
> Compare with $12.80 for the cheapest CycloneIII.

MAX II has 512*16 bit flash on board (good enough for a boot ROM),
Cyclone requires external flash. My devkit is MAX II ($100 full board
inc LCD unit).

> Okay, you probably want a secure bitstream. Spartan3A has that covered
> with their "Device DNA" trick. Digikey lists the XC3S50A-4TQ144C at
> $10.02 and it boots from a standard serial SPI flash. All pricing is
> in onesies.

Na a big feature will be JTAG reprogramming, and open VHDL (not
necessarily free). Custom reflashing is just part of the culture
possibilities. Cheap price, but the flash is external again, although
this maybe offset by external RAM cost. Low power is another MAX II
feature, getting battery powered performance. Not that it's a feature
needed by all, but headphone composition? Old SIM cards SMS space for
preset saving? (leave phone nums, as must not lose, good for sending
preset to others too.) The in system reprograming feature is also good
here, as self JTAGing between song setups.

> This is getting pretty far off-topic but it does illustrate that
> putting Forth in FPGAs is getting much more cost effective these days.
> Limited internal memory will favor Forth's shrewd use of resources for
> the next 10 years at least.

Ya it is the main reason over C.

cheers
jacko