Intellasys News?

I was wondering if there was any Intellasys news as of late for us
mortals?

Jason

Jason Damisch wrote:
> I was wondering if there was any Intellasys news as of late for us
> mortals?
>
> Jason

Depends on how up-to-date you are. A new VentureForth Programmer's
Manual (which I wrote) was posted on the web site in July, their
SwiftForth-based compiler has a new release which runs on either Windows
or Linux, and they will give free boards & software to anyone who
proposes an interesting project. I am advised there will be a new
announcement soon, maybe next month.

Go to www.intellasys.net and select any of the major buttons to get a
link to the manual, and see the Blog ("What would you do with a Forth
drive?") to find how to get a free evaluation board.

Cheers,
Elizabeth

--
==================================================
Elizabeth D. Rather (US & Canada) 800-55-FORTH
FORTH Inc. +1 310.999.6784
5959 West Century Blvd. Suite 700
Los Angeles, CA 90045
http://www.forth.com

"Forth-based products and Services for real-time
applications since 1973."
==================================================

This from the MPE site

"Chips are real, and Stephen has a 40 core chip to show at EuroForth
2008."

On Fri, 22 Aug 2008 22:35:21 -0700 (PDT), Jason Damisch
<jasondamisch@yahoo.com> wrote:

>"Chips are real, and Stephen has a 40 core chip to show at EuroForth
>2008."

40 was a typo, but there will be news at EuroForth 2008 in Vienna.
Until then, NDAs apply.

Stephen


--
Stephen Pelc, stephenXXX@mpeforth.com
MicroProcessor Engineering Ltd - More Real, Less Time
133 Hill Lane, Southampton SO15 5AF, England
tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691
web: http://www.mpeforth.com - free VFX Forth downloads

Jason Damisch wrote:
> I was wondering if there was any Intellasys news as of late for us
> mortals?
>
> Jason

Today's press release:

---------------------------

Sept. 24, 2008 13:00 UTC
IntellaSys’ 40-core Processor Technology Creates Industry Benchmark for
Embedded Applications

SEAforth 40C18 Multicore Processor Provides Orders of Magnitude
Improvements in Speed, Power and Size Over Competitive Offerings

CUPERTINO, Calif.--(BUSINESS WIRE)-- IntellaSys©, the technology
development arm of the TPL Group, today unveiled its industry-leading
SEAforth® 40C18 multicore processor technology for next-generation
embedded wireless, portable and distributed data processing
applications. The SEAforth 40C18 is an array of 40 fully functional CPUs
operating asynchronously on a monolithic die. Based on the IntellaSys
Scalable Embedded Array™ (SEA) platform, the SEAforth 40C18 technology
sets the performance paradigm of the future for high-speed parallel
execution capabilities, including superior performance per watt, low
power consumption and low cost benefits.

“The SEAforth 40C18 represents a major milestone in embedded design,”
said Chet Brown, Chief Executive Officer of IntellaSys. “There are no
central clock-tree inefficiencies. Each core can operate at up to 700
MHz while the chip dissipates an average of an unrivaled 150 milliwatts
in a typical application – and all this at one-tenth the cost of other
products in the market.”

The speed, power and size advantages of the SEAforth 40C18 design are
ideally suited for today’s high data throughput requirements in a wide
range of consumer electronics, networking, automotive and defense
applications. The chip is currently in beta testing at leading OEMs.
“Power consumption is an extremely critical factor when designing
devices for embedded automotive applications,” said Jeff Ota, Advanced
Technology Engineering, BMW Technology Office Palo Alto. “While running
tests on edge filtering for automotive imaging applications, we found
the SEAforth 40C18 delivers advanced filtering capabilities at a
fraction of the power consumed by other products available in the market
today.”

Featuring the smallest core size design (0.13 mm2), the SEAforth chip
consumes 28 times less power while running 240 times faster than
competing architectures. The SEAforth 40C18 breaks the memory bottleneck
by creating a RAM and ROM on each core. This enables individual cores to
run at the full native speed of the silicon instead of being throttled
down to a slower external system clock frequency. The automatic
synchronization feature between cores allows the processors to share the
computing load by talking to each other to pass data, status signals and
even code blocks. When individual CPUs are not active, they
automatically shut down or sleep, consuming just 5.4 µW in leakage
current until awakened.

“The beauty of this single-chip 40 CPU processing solution is that it is
completely programmable – meaning if a spec changes, it is a code issue,
not a silicon turn,” said Charles Moore, Chief Technology Officer of
IntellaSys. “With 40 cores operating independently on the chip,
designers can dedicate groups of them to handle specific tasks. For
example, some could be assigned compute-intensive Fast Fourier
Transforms (FFT) while others handle wireless connectivity, standard I/O
interfaces or drive external memory.”

The product will be offered with VentureForth™, an advanced multicore
integrated development environment (IDE) that includes fully interactive
programming, testing and debugging facilities. The SEAforth 40C18 is
capable of executing 80 percent of its VentureForth instructions in 1.38
nanoseconds while drawing 7mW of power or less per CPU.

The SEAforth 40C18 is slated for December 2008 availability. For details
on qualified availability and pricing of products and development
systems, please contact the company at sales@intellasys.net.
--------------------------------

I have been working on the documentation for this for a while (wrote the
VentureForth manual, edited the Data Sheet). It looks like a very nice
part. Evaluation quantities have been available for several months.

Cheers,
Elizabeth

--
==================================================
Elizabeth D. Rather (US & Canada) 800-55-FORTH
FORTH Inc. +1 310.999.6784
5959 West Century Blvd. Suite 700
Los Angeles, CA 90045
http://www.forth.com

"Forth-based products and Services for real-time
applications since 1973."
==================================================

> 40 was a typo, but there will be news at EuroForth 2008 in Vienna.
> Until then, NDAs apply.
>
> Stephen

Typo? :^)

The Intellasys site has changed. There are more .pdf files to look
at. This sounds really exciting.

http://www.intellasys.net/

Ofcourse I am a mere mortal, but I think that a Rad Hard version might
be really good for space apps, including construction robots for space
structures.

Jason

Jason Damisch wrote:
>> 40 was a typo, but there will be news at EuroForth 2008 in Vienna.
>> Until then, NDAs apply.
>>
>> Stephen
>
> Typo? :^)
>

Well, I don't know what Stephen has to show in Vienna, but I've had a
40-core part on my desk for a couple of months. It's a big improvement
over the S24 in many respects, including math features, much more I/O, etc.

Cheers,
Elizabeth

--
==================================================
Elizabeth D. Rather (US & Canada) 800-55-FORTH
FORTH Inc. +1 310.999.6784
5959 West Century Blvd. Suite 700
Los Angeles, CA 90045
http://www.forth.com

"Forth-based products and Services for real-time
applications since 1973."
==================================================

Elizabeth D Rather wrote:
> Featuring the smallest core size design (0.13 mm2), the SEAforth chip
> consumes 28 times less power while running 240 times faster than
> competing architectures.

For comparison, to argue a bit about Chucks tool chain vs. a standard tool
chain: With my current b16 project (with a 0.18µ TSMC-compatible process),
the CPU core is 0,035mm² large, and a memory with the size used in the
SeaForth chip is 0,040mm² large, total 0,075mm², about half the size of
their core (that's standard cells plus memory compiler). We have no speed
constraints in the project, so the synthesis just optimized for size, and
produced a core that could run 250MHz worst case. I'm sure I could get
something above 500MHz for typical operating conditions (don't know how
much), if I would need it. Of course Chuck's chip also contains the 4
communication ports, and additionally A and B registers, so maybe that
accounts for the additional 0.075mm². But my point is: I don't see the big
advantage of Chuck's tool, apart from that it is a lot less complicated
(but it makes designing the chip a lot more work than just writing a few
hundred lines of Verilog).

--
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/

On Thu, 25 Sep 2008 12:58:06 +1000, Elizabeth D Rather <erather@forth.com> wrote:

> Well, I don't know what Stephen has to show in Vienna, but I've had a
> 40-core part on my desk for a couple of months. It's a big improvement
> over the S24 in many respects, including math features, much more I/O, etc.
>
> Cheers,
> Elizabeth


Hi Elisabeth.

I have been snowed under for a number of months with another project, so have
not had the chance to investigate the s24 in depth. But I would like to ask
if you could share with us the improvements you see of the s40 versus the s24?

I am really curious about a few other things though, that you maybe able to
shed more light on.

It seems to bit bang serial from all coms/serial IO, requiring multiple
instruction cycles to form a word. Is there some mechanism that overcomes
this (or am I missing the obvious and it is just a tight loop with one cycle
per bit)?

Back in the early century, various memories types were to have different max
speeds. Will ROM code work faster?

What speed are they aiming at for execution from external memory?


I suppose that is all I can think of, the rest is pretty obvious.

It is a shame that they don't have interprocess communications running at
high enough speed to form 18 bits words per core cycle (among those design
suggestions I made a few months back, which I might be able to emulate in
code).

Well, I think the s40 will do, but love to see the future chips.


Thanks in advance Elisabeth

Wayne.