To explain simply, many.

The following URL is my current model for a super scalable computer (
designed for fault tolerant CYC large knowledge base server
architecture) ( full 16 way SMP MPP with "caching" crossbar
performance)
(
URL,
http://groups.google.com/group/sci.m...d2f119b8eeee56
USE: --show quoted text--
)

The following URL maybe for an end user home and office computing
architecture, ( crippled crossbar)
but may give more ON-CHIP cache for the sixteen diagonal nodes ( the 16
way SMP I have so often spoken)
(
URL,
http://groups.google.com/group/comp....e0906c30f94db8
)

History note, between the years of 1996-1999 my formulation was much
closer related to a sixteen way SMP of NOVIX/HARIS, then later SH-BOOM,
althought, I did read a BYTE article about the Novix chip in 1996, I
had not review SH-BOOM patents until 1998. Mr. Moore's 25X simply fit
my VLIW SMP MPP symmetry problem with a high performance caching
crossbar ( similar) circuit.

( OK for about seven years , I felt little more than the value of a
Cold Political War Correctness electronic eavesdropper information
extraction lab rat for Russia, but thats fictional novel of another
color. )

mawcowboy