Refactoring FPGA causes increase of SLICEs when converting codeblocks to subVIs?This is a discussion on Refactoring FPGA causes increase of SLICEs when converting codeblocks to subVIs? within the labview forums in Programming Languages category; Just wondering if this to be expected. I noticed that the SLICE count increased by about 500 (12700 -> 13200) when converting some code to sub VIs (using create sub VI). I created about 5 sub VIs with some basic logic in them. Theroretically there should be no difference..? I'm using a 3M crio 9104 backplane. Message Edited by robdevyogi on 08-15-2008 03:20 PM... | ||||||||
| | ||||||||
| ||||||||
| Register | FAQ | Calendar | Search | Today's Posts | Mark Forums Read |
|
#1
08-15-2008, 06:40 PM
| |||
| |||
 Refactoring FPGA causes increase of SLICEs when converting codeblocks to subVIs? Just wondering if this to be expected. I noticed that the SLICE count increased by about 500 (12700 -> 13200) when converting some code to sub VIs (using create sub VI). I created about 5 sub VIs with some basic logic in them. Theroretically there should be no difference..? I'm using a 3M crio 9104 backplane. Message Edited by robdevyogi on 08-15-2008 03:20 PM  |
 |
« Previous Thread
|
Next Thread »
| Thread Tools | |
| Display Modes | |
Linear Mode
All times are GMT -5. The time now is 05:47 PM.
