hi,

am about to develop a systolic array for performing multiplication & division..
so am suppose to write verilog codings for the following algorithm which resulted in error while trying..
can any one please help me with the verilog codings for the following Montgomery modular multiplication algorithm..

Input:x,y,m: m is odd, |x|< m, & |y|< m
output: z:z mod m = xy2^(-n-2)(mod m), & |z|<m
1. z<- 0;
2. for i <- 0 to n+1;
3. z <- MODDIV2FLAG(z+x(y[i-1]-y[i]),m);
-------------------thank u----------------------------------------