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Rating Thread / Thread Starter	Last Post	Replies	Views
complex defines..	Yesterday 07:00 AM	0	2
help on a complex macro	09-05-2008 06:07 PM	1	2
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Snooper Module in Verilog	09-05-2008 04:06 PM	1	2
VPI Module/Instance	09-05-2008 02:50 PM	0	1
help needed on a complex macro	09-05-2008 01:43 PM	1	2
FSDB to EVCD	09-05-2008 11:41 AM	0	2
Custom Clock Signals	09-05-2008 11:08 AM	8	9
[VPI] read and write values of register arrays ?	09-05-2008 10:28 AM	0	2
[VPI] read and write values of register arrays ?	09-05-2008 10:21 AM	0	2
SVA property question	09-05-2008 08:51 AM	0	2
`default net_type none	09-05-2008 07:22 AM	3	4
call for papers - ISQED09	09-04-2008 01:07 PM	0	2
Questasim Equivalent commands for Icarus Verilog	09-04-2008 08:06 AM	4	5
Re: SDIO open source	09-03-2008 06:38 PM	0	1
Fork-join clarification	09-03-2008 12:25 PM	2	3
request for beta testers -- TimingAnalyzer Program	09-03-2008 09:39 AM	0	2
verilog adders (verilog optimization) ( 1 2 3)	09-03-2008 08:18 AM	24	25
incrementing a 1-bit register?	09-03-2008 08:00 AM	9	12
[PLI] cbValueChange callback behavior at time 0	09-01-2008 09:08 PM	2	11
IEEE ISQED09 Call for Papers	09-01-2008 01:27 PM	0	2

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