verilog

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Threads in Forum : verilog

Rating Thread / Thread Starter	Last Post	Replies	Views
Gate Level Fault simulation using verilog rocketsingh	08-06-2010 06:44 PM by rocketsingh	0	47
Verilog code for a serial transmission unit Munazza	07-17-2010 04:03 AM by Munazza	0	75
Verilog code help for Floating Point Unit Application Development	07-13-2010 08:56 PM by arunareddy	2	4,009
Warning of testbench in Verilog Application Development	04-07-2010 06:52 AM by masterfish	6	1,002
Using Parameterized Macros gaurang4040	03-30-2010 09:09 AM by gaurang4040	0	149
dynamically enable/disable timing checks? usenet	03-24-2010 05:40 AM by elizas	8	917
missing in synthesis tools. fineshang	03-12-2010 10:39 PM by fineshang	0	123
some verilog basic questions jembutkeriting	03-09-2010 09:32 AM by vinod_cheedella	1	223
Is it possible to use generate in verilog with define files? gilgol	01-13-2010 04:27 AM by gilgol	0	398
Using Hhierarchical expressions RaviMarate	12-14-2009 04:26 AM by RaviMarate	0	265
how to use `celldefine in verilog Application Development	12-10-2009 01:35 PM by leochen75	5	1,469
fixed point multiplier and divider usenet	11-15-2009 03:33 PM by subedi	3	1,445
help with code toffee_pie	10-30-2009 02:06 PM by toffee_pie	1	182
newbie help to compile verilog code toffee_pie	10-26-2009 03:39 PM by toffee_pie	0	228
how to read and convert ascii file into bit vectors aravin	10-22-2009 06:49 AM by aravin	0	402
Concept on Blocking assignment and always jasonkee111	09-03-2009 12:20 AM by jasonkee111	0	299
SystemVerilog interface: virtual and ref usenet	08-20-2009 05:08 AM by tudorelu87	5	2,061
Asynchronous FIFO with odd depth navinks	06-26-2009 01:26 AM by navinks	0	551
Asynchronous FIFO with odd depth navinks	06-26-2009 01:02 AM by navinks	0	281
Question about automatic testbench tunger	06-25-2009 04:27 PM by tunger	0	279