verilog

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Threads in Forum : verilog

Rating Thread / Thread Starter	Last Post	Replies	Views
missing in synthesis tools. fineshang	03-12-2010 10:39 PM by fineshang	0	4
some verilog basic questions jembutkeriting	03-09-2010 09:32 AM by vinod_cheedella	1	116
Is it possible to use generate in verilog with define files? gilgol	01-13-2010 04:27 AM by gilgol	0	88
Using Hhierarchical expressions RaviMarate	12-14-2009 04:26 AM by RaviMarate	0	136
how to use `celldefine in verilog Application Development	12-10-2009 01:35 PM by leochen75	5	974
fixed point multiplier and divider usenet	11-15-2009 03:33 PM by subedi	3	906
help with code toffee_pie	10-30-2009 02:06 PM by toffee_pie	1	120
newbie help to compile verilog code toffee_pie	10-26-2009 03:39 PM by toffee_pie	0	159
how to read and convert ascii file into bit vectors aravin	10-22-2009 06:49 AM by aravin	0	220
Concept on Blocking assignment and always jasonkee111	09-03-2009 12:20 AM by jasonkee111	0	207
SystemVerilog interface: virtual and ref usenet	08-20-2009 05:08 AM by tudorelu87	5	1,402
Asynchronous FIFO with odd depth navinks	06-26-2009 01:26 AM by navinks	0	403
Asynchronous FIFO with odd depth navinks	06-26-2009 01:02 AM by navinks	0	209
Question about automatic testbench tunger	06-25-2009 04:27 PM by tunger	0	220
Online verilog projects wanted Mastermind_14	04-21-2009 03:31 AM by mingscians	1	983
Verilog testbench newbie question (modelsim) ktsangop	03-17-2009 01:44 PM by Arnica	1	1,498
Pipelined signed multipliers khodorf	03-03-2009 07:47 AM by khodorf	0	440
Compilation and simulation warning jasonkee111	02-24-2009 10:05 AM by jasonkee111	0	488
i is not constant jasonkee111	02-09-2009 07:38 PM by jasonkee111	0	258
systemverilog modports boldy00	02-06-2009 03:04 AM by boldy00	0	468