error in Synplify pro - verilog

The module you should specify for the "top module" is the verilog code
that starts wil "module" and ends with "endmodule" rather than the file
name. One file can contain many modules; SynplifyPro simply wants to
know which of these many modules across several files is top? Which
module specifies your pins?

srini wrote:
> Hi,
> When I am synthesizing using Synplify Pro, I am getting the following
> errors:
> 1. Internal error in m_xilinx
> 2. No component with name top_module.v
>
> Actually I have created a file called top_module.v and instantiated
> other modules in that file. I have included this file name in Top level
> module option in Implementation options. Is that wrong?

Hi,
The top_module.v is my TOP module in which I am instantiating all the
other modules. This will be the module that specifies my pins. Do I
have to include some pin information in my TOP module?

"srini" <g.shrinivasan@gmail.com> wrote in message
news:1144817093.047840.185190@z34g2000cwc.googlegroups.com...
> Hi,
> The top_module.v is my TOP module in which I am instantiating all the
> other modules. This will be the module that specifies my pins. Do I
> have to include some pin information in my TOP module?

There are modules and there are files.
top_module.v is a file.
In that file if you find:

module top_module ( input ...
full pin list
);
... // lots of code, some of which instantiates other modules

endmodule

then your top module is top_module, not the file top_module.v.

Synplify is NOT asking for the file that contains your top module.

Hi,
Synplify Pro carries out synthesis even if dont specify ant top module.
Then what is the significance of this option? Also there is a "extract
parameters" button. When I press this button, I am not seeing
difference in my window. How to use these options?

Thanks & Regards,
Srini.