assignment of a real value to a register... - verilog

On 21 Apr 2006 13:14:35 -0700, "kb33" <kanchan.devarakonda@gmail.com>
wrote:

>If I have 2 definitions in my verilog code:
>
>reg [31:0] result;
>real fp_result;
>
>then can I do the following (and synthesize)?
>
>// Compute the value of fp_result....
>
>//DO the following assignment...
>
>always @(posedge clk)
> result <= fp_result;

The reals in verilog are double precision so your reg has to be 64
bits and if you want to access the value of a real you need to use
$realtobits before you can copy it to a reg. But reals are not
synthesizable so you have to implement your own floating point
operators anyway.

Use "realtobits()" system function to accomplish the job

Joe
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

kb33 wrote:
> Hi,
>
> If I have 2 definitions in my verilog code:
>
> reg [31:0] result;
> real fp_result;
>
> then can I do the following (and synthesize)?
>
> // Compute the value of fp_result....
>
> //DO the following assignment...
>
> always @(posedge clk)
> result <= fp_result;
>
>
>
> Thanks,
>
> Kb33