Verilog Sythesis using Xilinx IS, help with RTL Coding Style, feedback : verilog

Hello All,

I'm about 3 weeks into learning Verilog using Xlinix 8.1 with a Virtex
4. I've been to all the major sites: fpga4fun.com, asic-world.com,
http://tutor.al-williams.com/wpv-1.htm (not working for me at the
moment), http://www.see.ed.ac.uk/~gerard/Teach/Verilog/, The Evita
Verilog Tutorial from Aldec, also some great articles from someone on
here, couldn't rememeber the Author or links, and a quick search didn't
turn them up. I did however find more info that I'm going to browse
through to get a better feel for the RTL style.

>From browsing around on here I noticed that it seems pretty common to
have a Reset port that helps to initialize values, with the exception
of that and some other things what do you think of my code. I know
there is a lot to be done to shorten it up, and make it work, but give
me some constructive feedback to work with while I search around and
try to clean it up (and make it work!)

I think there might be some race conditions happening here as well. If
anyone has some insight.

I am trying to send 3, 24-bit data words into the Program module that
performs a serial conversion and some control logic and then outputs
them individually.

module radar_module(
clk200, // 200MHz clock input (for AD4360 20MHz clock generation)
Control, // Control Lines from com_module
DataOut_8, // AD4360-8 serial data out
LE_8, // AD4360-8 Latch Enable (low to transmit data)
clk20 // AD4360 20MHz clock
);

input clk200;
input [3:0] Control;
output DataOut_8;
output LE_8;
output clk20;

reg [23:0] ProgrammingWord;
reg cnt1 = 1;
reg start_8;

always @ (posedge clk200)
begin
case (Control)
4'b0011: // Power Up Sequence
begin
case (cnt1)
1:
begin
ProgrammingWord <= 24'b10010100_00000000_00001100; // data1
start_8 <= 1; // Start Transmission
cnt1 <= 2; // next
end
2:
begin
start_8 <= 0;
cnt1 <= 3; // next
end
3:
begin
ProgrammingWord <= 24'b00000100_10001111_11110000; // data2
start_8 <= 1; // Start Transmission
cnt1 <= 4; // next
end
4:
begin
start_8 <= 0;
cnt1 <= 5; // next
end
5:
begin
ProgrammingWord <= 24'b01000000_00010010_00000000; // data3
start_8 <= 1; // Start Transmission
cnt1 <= 6; // next
end
6: start_8 <= 0; // End transmission
default: ; // Do Nothing
endcase
end
endcase
end



// Modules
Program AD4360_8(
clk200,
(start_8 & ~busy),
ProgrammingWord,
clk20,
DataOut_8,
LE_8,
busy
);

endmodule