Inferring Xilinx synthesis results - Help required! : verilog

Hi,
My design has to work at around 65MHz.When I synthesize, the report
shows that the minimum clock period is 39MHz. Does it mean that my
design does not meat the timing contraints? How to check whether my
design is meeting the timing?
Actually I am getting an input clock which I am multiplying it thru DCM
to get this 65MHz clock and using it my design. In the constraints
editor, only the clock to the FPGA is appearing and I dont know how to
specify the freq. for the output clock from the DCM. I feel that since
the input clock freq. is low, its not applying the constraints properly
to the rest of the design which has to work at around 65Mhz. I dont
know whether I am correct. Plz let me know the correct procedure.

Thanks & Regards,
Srini.

If your DCM generates a 65 MHz clock from a 10 MHz reference, specify the
*input* clock as 10 MHz, not 65. The Xilinx Timing ****yzer can provide
detailed information on your failing paths. Look into the capabilities of
that tool.

"srini" <g.shrinivasan@gmail.com> wrote in message
news:1147185539.274090.195340@j73g2000cwa.googlegroups.com...
> Hi,
> My design has to work at around 65MHz.When I synthesize, the report
> shows that the minimum clock period is 39MHz. Does it mean that my
> design does not meat the timing contraints? How to check whether my
> design is meeting the timing?
> Actually I am getting an input clock which I am multiplying it thru DCM
> to get this 65MHz clock and using it my design. In the constraints
> editor, only the clock to the FPGA is appearing and I dont know how to
> specify the freq. for the output clock from the DCM. I feel that since
> the input clock freq. is low, its not applying the constraints properly
> to the rest of the design which has to work at around 65Mhz. I dont
> know whether I am correct. Plz let me know the correct procedure.
>
> Thanks & Regards,
> Srini.
>

I have specified the input clock freq. as 10 MHz only in the
constraints editor. The synthesis report shows the minimum period to be
39 Mhz. But the timing ****yzer shows the worst case path delay to be
14.5 ns which meets my timing constraint of around 15ns. I was of the
opinion that if the worst case path delay meets the timing constraint,
then my design will work at the required freq.(65 MHz). Am I wrong?
What does the min. period value in the syntehsis report signify?

Thanks & Regards,
Srini.

srini wrote:

> I have specified the input clock freq. as 10 MHz only in the
> constraints editor. The synthesis report shows the minimum period to be
> 39 Mhz. But the timing ****yzer shows the worst case path delay to be
> 14.5 ns which meets my timing constraint of around 15ns. I was of the
> opinion that if the worst case path delay meets the timing constraint,
> then my design will work at the required freq.(65 MHz). Am I wrong?
> What does the min. period value in the syntehsis report signify?
>
> Thanks & Regards,
> Srini.

If you run timing ****yzer, you can see the paths that are failing.
These paths are annotated with the required and actual timing values
with full disclosure on where the required timing comes from. If you
have a rising edge generated signals feeding falling edge clocked logic,
your cycle time will be cut in half and well documented in the Timing
****yzer results for your ****yzed paths.

Shouldn't you be looking at the place and route report instead of the
synthesis report as it is just an estimation.


srini wrote:
> I have specified the input clock freq. as 10 MHz only in the
> constraints editor. The synthesis report shows the minimum period to be
> 39 Mhz. But the timing ****yzer shows the worst case path delay to be
> 14.5 ns which meets my timing constraint of around 15ns. I was of the
> opinion that if the worst case path delay meets the timing constraint,
> then my design will work at the required freq.(65 MHz). Am I wrong?
> What does the min. period value in the syntehsis report signify?
>
> Thanks & Regards,
> Srini.