Tristate buffer simulations - verilog

This is a discussion on Tristate buffer simulations - verilog ; Hi, Assuming I have this tristate open drain buffer defined as (my library has this buffer) assign out = en ? 1'bz : 1'b0; Now I want to simulate this buffer. The way I try is to connect two such ...

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Tristate buffer simulations

  1. Default Tristate buffer simulations

    Hi,

    Assuming I have this tristate open drain buffer defined as (my library
    has this buffer)

    assign out = en ? 1'bz : 1'b0;

    Now I want to simulate this buffer. The way I try is to connect two
    such buffers, e.g.,

    tribuffer tri1(.out(out), .en(en1));
    tribuffer tri2(.out(out), .en(en2));

    tribuffer is the module name and I define en1 and en2 as regs and out
    as tri. Outlining all combinations of en1 and en2, I can only get out
    is either 0 or z. Never seen out = 1.

    My question is that how can I specify out is a pullup wire (or maybe
    other types) to obtain 1? Or if this way is not a doable way to test
    it, what is the better way to test it?

    Thanks.


  2. Default Re: Tristate buffer simulations

    Hi,

    a pull up can describe like this:

    wire (weak1,weak0) out = 1'b1;

    rgds

    Verictor a écrit :
    > Hi,
    >
    > Assuming I have this tristate open drain buffer defined as (my library
    > has this buffer)
    >
    > assign out = en ? 1'bz : 1'b0;
    >
    > Now I want to simulate this buffer. The way I try is to connect two
    > such buffers, e.g.,
    >
    > tribuffer tri1(.out(out), .en(en1));
    > tribuffer tri2(.out(out), .en(en2));
    >
    > tribuffer is the module name and I define en1 and en2 as regs and out
    > as tri. Outlining all combinations of en1 and en2, I can only get out
    > is either 0 or z. Never seen out = 1.
    >
    > My question is that how can I specify out is a pullup wire (or maybe
    > other types) to obtain 1? Or if this way is not a doable way to test
    > it, what is the better way to test it?
    >
    > Thanks.
    >


  3. Default Re: Tristate buffer simulations

    I am not sure I can specify "out" be 1'b1 while it is sure doable to
    define it is a pullup. This is because the buffer is an open drain
    bidirectional wire.


    On Jan 24, 12:50 am, Jerome <jeje@.com> wrote:
    > Hi,
    >
    > a pull up can describe like this:
    >
    > wire (weak1,weak0) out = 1'b1;
    >
    > rgds
    >
    > Verictor a écrit :
    >
    >
    >
    > > Hi,

    >
    > > Assuming I have this tristate open drain buffer defined as (my library
    > > has this buffer)

    >
    > > assign out = en ? 1'bz : 1'b0;

    >
    > > Now I want to simulate this buffer. The way I try is to connect two
    > > such buffers, e.g.,

    >
    > > tribuffer tri1(.out(out), .en(en1));
    > > tribuffer tri2(.out(out), .en(en2));

    >
    > > tribuffer is the module name and I define en1 and en2 as regs and out
    > > as tri. Outlining all combinations of en1 and en2, I can only get out
    > > is either 0 or z. Never seen out = 1.

    >
    > > My question is that how can I specify out is a pullup wire (or maybe
    > > other types) to obtain 1? Or if this way is not a doable way to test
    > > it, what is the better way to test it?

    >
    > > Thanks.- Hide quoted text -- Show quoted text -



  4. Default Re: Tristate buffer simulations

    On Jan 23, 8:29 pm, "Verictor" <stehu...@gmail.com> wrote:
    > My question is that how can I specify out is a pullup wire (or maybe
    > other types) to obtain 1? Or if this way is not a doable way to test
    > it, what is the better way to test it?



    This way is fine. At the top-level, declare out as a tri1, not a wire.

    -cb


  5. Default Re: Tristate buffer simulations


    Chris Briggs wrote:
    >
    > This way is fine. At the top-level, declare out as a tri1, not a wire.


    Yes, that will give you an implicit pullup. Or you can specify an
    explicit pullup using a pullup primitive. Or you can do as another
    poster suggested and add a continuous assignment to act as the
    pullup (though the usual strength for a pullup is pull, not weak).

    As an alternative to your continuous assignment that explicitly
    drives a Z value on the net when the en is true, you can use a
    continuous assignment that just assigns the output to be the
    input, but with appropriate strength values:

    assign #(highz1, strong0) out = en;

    This has definite advantages for multi-bit buses. Your tristate
    buffer will only work for one bit. A continuous assignment with
    a drive strength value can handle an entire vector, and will
    put a z on all the bits that are 1, and a 0 on the ones that are 0.

    It will also be more accurate in its handling of the case where
    the en is X. With your model, the output will be a full-strength X.
    With the proper strength modeling, you will get a more accurate
    X that is known to be in the more limited range of strong0 to
    highz. If there is another driver driving a definite strong0, then
    the result will be a 0, as it should be. With your model, the
    result would come out X.

    If you are using this approach, you can build in the effect of a
    pullup with each driver by changing the highz1 to a pull1.

    Or you could go completely abstract and forget about the
    strengths, highz values and pullups. Just declare the net to
    be a wand (wire-and) net and use normal drivers on it. The
    net will resolve with a wire-and.

    Verilog allows a lot of flexibility in how you can model this for
    simulation. What approach you take may depend on what
    other tools you need to use, and what they will accept.


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