Include file extension: ".v" vs ".vh"? - verilog
This is a discussion on Include file extension: ".v" vs ".vh"? - verilog ; I've seen both ".v" and ".vh" used as extensions for
`include files. Although Verilog doesn't care about the
extension name at all I'm wondering what people in this
group prefer.
Is it common to use ".vh"? I've only seen it ...
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Include file extension: ".v" vs ".vh"?
I've seen both ".v" and ".vh" used as extensions for
`include files. Although Verilog doesn't care about the
extension name at all I'm wondering what people in this
group prefer.
Is it common to use ".vh"? I've only seen it in a couple
of places, whereas I've seen ".v" in lots of designs at
for example opencores.
/Andreas
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Re: Include file extension: ".v" vs ".vh"?
On May 4, 2:54 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> I've seen both ".v" and ".vh" used as extensions for
> `include files. Although Verilog doesn't care about the
> extension name at all I'm wondering what people in this
> group prefer.
>
> Is it common to use ".vh"? I've only seen it in a couple
> of places, whereas I've seen ".v" in lots of designs at
> for example opencores.
>
> /Andreas
For me it depends on what's in the file I'm including.
I hadn't seen the .vh convention, but I use .v when
there is behavioral code in the file, mostly to convice
the editor to properly format and keyword highlight, etc.
When the file is only `define etc. I usually use a .inc
(include) file extension. This helps recognize the
file as something that is not compilable by itself.
Mostly I try not to use `include if I can avoid it.
Regards,
Gabor
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Re: Include file extension: ".v" vs ".vh"?
On May 4, 2:54 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> I've seen both ".v" and ".vh" used as extensions for
> `include files. Although Verilog doesn't care about the
> extension name at all I'm wondering what people in this
> group prefer.
>
> Is it common to use ".vh"? I've only seen it in a couple
> of places, whereas I've seen ".v" in lots of designs at
> for example opencores.
I have typically used .v
FYI, SystemVerilog supports packages that can be loaded with the
import keyword, much like a C++ namespace. Depending on which tools
you have access to, you may want to check that out.
Edmond
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Re: Include file extension: ".v" vs ".vh"?
On May 3, 11:54 pm, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> I've seen both ".v" and ".vh" used as extensions for
> `include files. Although Verilog doesn't care about the
> extension name at all I'm wondering what people in this
> group prefer.
I've seen .vh used for Verilog header files, containing `defines, and
`included in other .v files.
David
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Re: Include file extension: ".v" vs ".vh"?
gabor <gabor@alacron.com> writes:
> Mostly I try not to use `include if I can avoid it.
Ditto.
Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
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Re: Include file extension: ".v" vs ".vh"?
I'm a VERY new Verilog user, doing a behavioral simulation of a microprogrammed CPU, and the little-bitty op cods need to be passed back and forth everywhere.
If include files are bad things, what is the preferred was to define something in one place and use it everywhere else?
- Mike
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