What is the meaning of dangling wire? - verilog

This is a discussion on What is the meaning of dangling wire? - verilog ; Sorry for the same. But I seem to be confused with the construct...

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What is the meaning of dangling wire?

  1. Default What is the meaning of dangling wire?

    Sorry for the same.
    But I seem to be confused with the construct


  2. Default Re: What is the meaning of dangling wire?

    On Aug 28, 6:37 am, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
    wrote:
    > Sorry for the same.
    > But I seem to be confused with the construct


    basically a net that is not doing it's job.

    i think it is a net that is not connected to an input
    or a net that is not connected to an input and output.






  3. Default Re: What is the meaning of dangling wire?

    Are you talking of something like this

    module top ( input a );
    endmodule




  4. Default Re: What is the meaning of dangling wire?

    On Aug 30, 8:54 am, "parag_p...@hotmail.com" <parag_p...@hotmail.com>
    wrote:
    > Are you talking of something like this
    >
    > module top ( input a );
    > endmodule



    That would be one example. It doesn't need to be in a module port
    list.
    In Verilog you can also have wires that are neither driven nor used.

    More examples:

    module top ( input a );
    wire b
    wire c
    assign c = 1'b1;
    endmodule

    Here a is an unused input, presumably driven exernally. This
    and c, which has an assignment but doesn't appear on the RHS
    of any expression, are examples of wires with one end dangling.
    Wire b is completely unconnected or dangling at both ends if
    you like to think of it that way. Normally this example
    would give warnings for each case, but no errors. Synthesis
    tools may give you an error due to the complete lack of
    synthesized logic in this example, but in the presence of
    other normal logic, this would again just create warnings.


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