How to implement VHDL 'transaction in verilog HDL? - verilog

On Oct 31, 2:22 pm, vishnuprasa...@gmail.com wrote:
> How to implement <signal>'transaction which is there in VHDL can be
> implemented in verilog HDL?

For the 0->1 transistion: @(posedge <signal>)
For the 1->0 transistion: @(negedge <signal>)

On Wed, 31 Oct 2007 03:14:05 -0700, muthusnv@gmail.com wrote:

>On Oct 31, 2:22 pm, vishnuprasa...@gmail.com wrote:
>> How to implement <signal>'transaction which is there in VHDL can be
>> implemented in verilog HDL?
>
>For the 0->1 transistion: @(posedge <signal>)
>For the 1->0 transistion: @(negedge <signal>)

This might work in simple cases, but you need to be careful.
S'transaction is a new signal, of type bit. It toggles when an
assignment was made to S, even if (a) S doesn't change as a result of
the assignment, and (b) when the assignment is a change that wouldn't
be detected by posedge or negedge (an X-equivalent to a Z-equivalent,
for example, toggles the new signal, but wouldn't be detected by
posedge or negedge).

The author probably had a good reason to use 'transaction, so you may
have to do something complicated to convert it (manually create a
named event, for example). You should post some code if it's a
problem.

Evan

On Oct 31, 1:22 am, vishnuprasa...@gmail.com wrote:
> How to implement <signal>'transaction which is there in VHDL can be
> implemented in verilog HDL?

There is no equivalent. The 'transaction can detect assignments which
do not change the value of the signal. This is apparently intended
for abstract modeling above the actual hardware level, where a
transaction represents passing a value over a bus but abstracting away
the handshaking that would be required in hardware. Verilog signals
are intended to represent actual hardware, where a non-change is not
detectable. The closest you could get to this abstract handshaking
would be to create a named event and trigger it when sending a
"transaction" on the signal.