Verilog 2001 Multidemensional arrays with real : verilog
This is a discussion on Verilog 2001 Multidemensional arrays with real within the verilog forums in Programming Languages category; Dear Experts outside, I'm starting with verilog 2001 and coded this: real edges [0:2][0:3]; edges = { { 0 , 0.5 ,0 , 3 } , //AT0 { 0 , 0.2 ,0 , 3 } , //SW3 { 0 , 0.1 ,0 , 3 } //SW2 }; What I would like to achive is a two dimensional array of real values. The compiler complaines at 0.5 in line 3 of the code listed here. I'm using ncverilog: 06.20-p001 with tells me: edges = { | ncvlog: *E,EXPLPA (_uif/Stimulus.v,8|6): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]. (`include file: _uif/Stimulus.v line 8, file: ...
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#1
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| I'm starting with verilog 2001 and coded this: real edges [0:2][0:3]; edges = { { 0 , 0.5 ,0 , 3 } , //AT0 { 0 , 0.2 ,0 , 3 } , //SW3 { 0 , 0.1 ,0 , 3 } //SW2 }; What I would like to achive is a two dimensional array of real values. The compiler complaines at 0.5 in line 3 of the code listed here. I'm using ncverilog: 06.20-p001 with tells me: edges = { | ncvlog: *E,EXPLPA (_uif/Stimulus.v,8|6): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)]. (`include file: _uif/Stimulus.v line 8, file: tb.v line 6) { 0 , 0.5 ,0 , 3 } , //AT0 | Does anyone know how to make ith right ?? Thanks Rolf |
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#2
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| On Sat, 8 Dec 2007 08:46:49 -0800 (PST), RolfK <Rolf.Kemper@eu.necel.com> wrote: >Dear Experts outside, > >I'm starting with verilog 2001 and coded this: Are you using +v2k on your command line? |
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#3
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| On 9 Dez., 18:52, mk <kal*@dspia.*comdelete> wrote: > On Sat, 8 Dec 2007 08:46:49 -0800 (PST), RolfK > > <Rolf.Kem...@eu.necel.com> wrote: > >Dear Experts outside, > > >I'm starting with verilog 2001 and coded this: > > Are you using +v2k on your command line? No, I understood that NC-Verilog will understand it anyhow. Meantime I know that the declaration is OK , but the assignment not. As I have written a code generator I assigned the values one by one in an initila routine. Not nice, but works. Rolf |
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#4
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| RolfK wrote: > On 9 Dez., 18:52, mk <kal*@dspia.*comdelete> wrote: >> On Sat, 8 Dec 2007 08:46:49 -0800 (PST), RolfK >> >> <Rolf.Kem...@eu.necel.com> wrote: >>> Dear Experts outside, >>> I'm starting with verilog 2001 and coded this: >> Are you using +v2k on your command line? > > No, I understood that NC-Verilog will understand it anyhow. > Meantime I know that the declaration is OK , > but the assignment not. As I have written a code generator I assigned > the values one by one in an initila routine. > Not nice, but works. > > Rolf I wasn't even aware that one could have an array of reals, but it seems to work in Modelsim. But, like you say, you have to initialize it one value at a time with an initial construct. You might also be able to use $fscanf to read real values from a text file and initialize the array. -Kevin |
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#5
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| On Dec 9, 2:03 pm, RolfK <Rolf.Kem...@eu.necel.com> wrote: > On 9 Dez., 18:52, mk <kal*@dspia.*comdelete> wrote: > > > Are you using +v2k on your command line? > > No, I understood that NC-Verilog will understand it anyhow. That is correct. NC-Verilog assumes Verilog-2001 by default. > Meantime I know that the declaration is OK , > but the assignment not. Verilog does not have the concept of an array initializer like C (though SystemVerilog does). |
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