SystemVerilog: declare and initialize arrays like in C? : verilog

I can't seem to find any mention of this in the LRM but I have to
believe you can do C-like array init. at declaration time. Can someone
steer me straight on this? I'd like to do something like this:

typedef bit [10:0] some_hw_reg_t;

some_hw_reg_t hw_reg[] = { 'h11, 'h12, 'h14, 'h20 };

but of course { term, term, ... } is concatenation not initaization.
So is there a way? How?

Thanks,

- Mark

You can use '{}, as in:

some_hw_reg_t hw_reg[4] = '{ 'h11, 'h12, 'h14, 'h20 };

-cb

On Dec 21, 2:09 pm, Chris Briggs <ch...@engim.com> wrote:
> You can use '{}, as in:
>
> some_hw_reg_t hw_reg[4] = '{ 'h11, 'h12, 'h14, 'h20 };
>
> -cb

Agh! I was missing a tiny ' symbol! Thank you, all is well now.

- Mark

On Dec 21, 2:09 pm, Chris Briggs <ch...@engim.com> wrote:
> You can use '{}, as in:
>
> some_hw_reg_t hw_reg[4] = '{ 'h11, 'h12, 'h14, 'h20 };

Some comments:

The ' was added to the C syntax to distinguish it from the Verilog
concatenation syntax, because it could be ambiguous which was meant in
some situations.

The choice of ' comes from the syntax type_name'{...}, which creates
an aggregate value of type type_name. This in turn comes from the
syntax for a type cast. In the context of an assignment, where the
type can be inferred from the type of the left-hand-side, the explicit
type can be left off, leaving just the '{...} behind.

Also note that Chris added the explicit size. Unlike C, you cannot
leave the size out and have it inferred from the number of elements on
the RHS. There are several reasons for that. One is that the empty
[] is the SystemVerilog syntax for a dynamic array. Another is that
the '{...} syntax does not require specifying all the elements
individually, allowing you to specify some elements individually, and
apply various default mechanisms to the rest. This means that you
cannot necessarily derive the number of elements from it.

sharp@cadence.com wrote:
> On Dec 21, 2:09 pm, Chris Briggs <ch...@engim.com> wrote:
>> You can use '{}, as in:
>>
>> some_hw_reg_t hw_reg[4] = '{ 'h11, 'h12, 'h14, 'h20 };
>
> Some comments:
>
> The ' was added to the C syntax to distinguish it from the Verilog
> concatenation syntax, because it could be ambiguous which was meant in
> some situations.
>
> The choice of ' comes from the syntax type_name'{...}, which creates
> an aggregate value of type type_name. This in turn comes from the
> syntax for a type cast. In the context of an assignment, where the
> type can be inferred from the type of the left-hand-side, the explicit
> type can be left off, leaving just the '{...} behind.
>
> Also note that Chris added the explicit size. Unlike C, you cannot
> leave the size out and have it inferred from the number of elements on
> the RHS. There are several reasons for that. One is that the empty
> [] is the SystemVerilog syntax for a dynamic array. Another is that
> the '{...} syntax does not require specifying all the elements
> individually, allowing you to specify some elements individually, and
> apply various default mechanisms to the rest. This means that you
> cannot necessarily derive the number of elements from it.

This is good to know. But I'm confused about the index. Does the above
declaration mean

some_hw_reg_t hw_reg[4] = 'h11;
some_hw_reg_t hw_reg[5] = 'h12;
some_hw_reg_t hw_reg[6] = 'h14;
....
?

-Kevin

On Jan 2, 2:08 pm, Kevin Neilson <kevin_neil...@removethiscomcast.net>
wrote:
>
> This is good to know.  But I'm confused about the index.  Does the above
> declaration mean
>
> some_hw_reg_t hw_reg[4] = 'h11;
> some_hw_reg_t hw_reg[5] = 'h12;
> some_hw_reg_t hw_reg[6] = 'h14;
> ...
> ?

No. None of the elements you refer to here exist. The declaration

some_hw_reg_t hw_reg[4];

is a C-like shorthand added in SystemVerilog to mean

some_hw_reg_t hw_reg[04-1)];

It is like C in that it creates 4 elements, with indexes starting at
0, and therefore ending at (4-1) or 3. And the initializer starts
with the left-hand index first. So it means something like

some_hw_reg_t hw_reg[0:3];
hw_reg[0] = 'h11;
hw_reg[1] = 'h12;
hw_reg[2] = 'h14;
hw_reg[3] = 'h20;