OK i found my mistake on the previous testbench.
My testbench created a posedge every 10 ns and the inputs every 5ns. So only half of them were triggering the module...
I have a new question now which i posted in a new thread about 6 days ago but it seems that my thread never made it...don't know why..?
Anyway, i have the same shift register code :
module fifo1 (C, SI, SO);
reg [7:0] tmp;
always @(posedge C)
tmp = tmp << 1;
tmp = SI;
assign SO = tmp;
I want to create multiple instances of the fifo1 modules which are interconnected with eachother. They will all have the same clock and do the same job plus the output of every shift register will provide the input to the next one. Just like the image below :
Can somebody please help me on how to do this using the generate/endgenerate statements?
Thanks in advance!