Verilog testbench (in modelsim) newbie question - verilog

Hi everyone!
This is my first post here. My name is Kostas and i use verilog (for the first time) for a university project...
Although i understand designs and testbenches from other people, i have a problem writing my own...

To the point.
I have a simple shift register design :

module fifo1 (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;

always @(posedge C)
begin
tmp = tmp << 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule

I am trying to test this on modelsim with the following testbench :

module fifo1_tb;
reg C,SI;
wire SO;

fifo1 DUT(C,SI,SO);

initial
begin
C=0;
SI=0;
end

initial
begin
$monitor(" OUTPUT : %b",SO);
end

always #5 C=!C;

initial
begin
#5 SI=1; #5 SI=0; #5 SI=1; #5 SI=0; #5 SI=1; #5 SI=0; #5 SI=1;
#5 SI=0; #5 SI=1; #5 SI=0; #5 SI=1; #5 SI=0; #5 SI=1;
#5 SI=0; #5 SI=1;
end

initial #100 $finish;

endmodule

The problem is that when i run this i get the following results :
# OUTPUT : x
# OUTPUT : 1
# ** Note: $finish : C:/Program Files/Modeltech_6.2b/My projects/FIFO1_tb.v(27)
# Time: 100 ns Iteration: 0 Instance: /fifo1_tb

Is this correct? Why does it stop after showing output : 1?
I was expecting that after 7 times of shift the output would be 1010101....and so on like the input i provided. But it is not shown there

Also i cannot view the signals of my design when i load the testbench simulation. So i cannot add them to the wave panel to monitor them over there..

Can you find anything wrong in my code? Please give me a hand.
Thanks in advance


p.s. I tested the design in Altera Quartus II where you can draw waves and a testbench isn't required and it seems to work fine there.