Continuous assignment vs. always blocks

I am using an Altera FPGA for my design. I have a bunch of
combinatorial logic that I tried to compile in Quartus using two
different approaches:
The first approach had only continuous assignments, though it looked
quite ugly (visually speaking) due to 3-4 of "?" conditions involved
in the statements.
In the second approach, I put the same logic in an "always" block, and
put a case statement inside the "always" block to take care of all the
conditions.

My observation was that in the first case, my logic used up 225 Logic
elements in the Altera device, and in the second case, this number
went up to 288, even though the code looked much cleaner.

Any comments? Is it really bad to use too many conditions in a
continuous assignment statement?

kb33

On Aug 6, 9:58 am, kb33 <kanchan.devarako...@gmail.com> wrote:
> I am using an Altera FPGA for my design. I have a bunch of
> combinatorial logic that I tried to compile in Quartus using two
> different approaches:
> The first approach had only continuous assignments, though it looked
> quite ugly (visually speaking) due to 3-4 of "?" conditions involved
> in the statements.
> In the second approach, I put the same logic in an "always" block, and
> put a case statement inside the "always" block to take care of all the
> conditions.
>
> My observation was that in the first case, my logic used up 225 Logic
> elements in the Altera device, and in the second case, this number
> went up to 288, even though the code looked much cleaner.
>
> Any comments? Is it really bad to use too many conditions in a
> continuous assignment statement?
>
> kb33

It shouldn't matter. A good synthesis tool should resolve it, to the
same logic. I'd verify that your case statement does not imply a
priority decoder? Which will happen if you don't write a fully
qualified case structure (or cheat using pragmas).

-Ryan