printing capital hex values in file

Hi
I am usingn $fdisplay to write values of register in files using %h or
%x modifier. But this writes number in lowercase like 5ab..fee...and
not 5AB or FEE. Is it possible to print number in capital?

Sorry if question sounds stupid. But in C language it is possible if
we use %X modifier..

Regards
Sandeep
Engineer

On Aug 7, 4:35 am, sandeep <sandeepkumar....@gmail.com> wrote:
> Hi
> I am usingn $fdisplay to write values of register in files using %h or
> %x modifier. But this writes number in lowercase like 5ab..fee...and
> not 5AB or FEE. Is it possible to print number in capital?
>
> Sorry if question sounds stupid. But in C language it is possible if
> we use %X modifier..
>
> Regards
> Sandeep
> Engineer

I don't think %x is proper for Verilog...

Did you try %H ?

On Aug 7, 12:39*pm, gabor <ga...@alacron.com> wrote:
> I don't think %x is proper for Verilog...
>
> Did you try %H ?

Doesn't work either. This has always bugged me about Verilog. In
your case, since you're dumping to a file you could post-process the
file. Otherwise, if you're using SystemVerilog and you HAVE to have
it you could do something like:

module toupper;
localparam N=16;
reg [N-1:0] junk;

function string toupper(
input [N-1:0] junk);

string lower;

$sformat(lower, "%x", junk);

return lower.toupper();
endfunction//toupper

initial begin
junk = 16'hABCD;
$display("%X", junk);
$display("%s", toupper(junk));
end
endmodule//toupper

On modelsim:

>vlog -sv toupper.v
>vsim -c work.toupper -do "run -all;quit -f"
...
# // ModelSim SE 6.2h May 17 2007
...
# run -all
# abcd
# ABCD
# quit -f

On Aug 9, 1:55*am, SysTom <tjo...@echelon.com> wrote:
> On Aug 7, 12:39*pm, gabor <ga...@alacron.com> wrote:
>
> > I don't think %x is proper for Verilog...
>
> > Did you try %H ?
>
> Doesn't work either. *This has always bugged me about Verilog. *In
> your case, since you're dumping to a file you could post-process the
> file. *Otherwise, if you're using SystemVerilog and you HAVE to have
> it you could do something like:
>
> module toupper;
> * * localparam N=16;
> * * reg [N-1:0] junk;
>
> * * function string toupper(
> * * * * input [N-1:0] junk);
>
> * * * * string * * *lower;
>
> * * * * $sformat(lower, "%x", junk);
>
> * * * * return lower.toupper();
> * * endfunction//toupper
>
> * * initial begin
> * * * * junk = 16'hABCD;
> * * * * $display("%X", junk);
> * * * * $display("%s", toupper(junk));
> * * end
> endmodule//toupper
>
> On modelsim:
>
> >vlog -sv toupper.v
> >vsim -c work.toupper -do "run -all;quit -f"
>
> ...
> # // *ModelSim SE 6.2h May 17 2007
> ...
> # run -all
> # abcd
> # ABCD
> # quit -f

Hi
Thanks for suggestion. Unfortunately in our company we are still using
Verilog for writing RTL.
I realiase it is not possible to do in Verilog, hence modified the C
model to print in lowercase, since my target was to compare the file
generated by C and verilog.
Regards

sandeep wrote:

> Thanks for suggestion. Unfortunately in our company we are still using
> Verilog for writing RTL.
> I realiase it is not possible to do in Verilog, hence modified the C
> model to print in lowercase, since my target was to compare the file
> generated by C and verilog.

Or use diff -i.

At least GNU diff has that, which is available for most
unix systems and for Windows systems.

-- glen