Any ModelSim SE or VCSi experts available to answer a question?

I have recently switched companies. All my experince is in using the Cadence
tools.
My new company uses both ModelSim and VCSi.

I have a golden VCD file generated from ModelSim and a VCD file generated by
VCSi.
When the files are compared there is a difference of 1417 signals which
exists in the ModelSim file but not the VCSi file.
I have now tracked ~50 of the signals down and found them to be parameters
that ModelSim dumps out but VCSi does not.
There is a high probability that all the 1417 signals are parameters.
Tracking them all down would be a pain.


Does anyone know an option in ModelSim that will turn parameter dumping to
the VCD file off?

or

Does anyone know an option in VCSi that will turn parameter dumping on?

I would prefer an option to VCSi but an option for ModelSim would be
workable?

I use VCS, not VCSi, but Synopsys added parameter dumping to VCS in
one of the later releases, either 2006.06-SP1 or 2006.06-SP2 I think.
What version of VCSi are you using?

You can also ask at vcs_support@synopsys.com or ask Mentor if you can
turn it off in Modelsim.

Of course, this begs the question: why are you comparing waves files?
Are you seeing different behavior from the two simulators or is it
that you consider one to be golden and compare the other one to it? If
the latter, you really should make your testbenches self-checking.
It'll make your life much easier.

-cb

VCS version: Y-2006-06-SP1

I have my company vendor contact asking the same questions as well, but this
group has a large amount of knowledge that may short cut the email bounce
time.

We are seeing difference in simulator operations. Our IP passes the self
checking test bench in one simnulator and fails in the other. The failure
was tracked down and required a coding style change to work-around. This
generated concern about any hidden coding style issues. Thus a full VCD
dump of the design in both simulators and comparison of the vcds was
ordered.
I, as the new guy, got the task.


"Chris Briggs" <chris@engim.com> wrote in message
news:e09ad3e4-167d-485f-bf3e-41bfefbb06d5@z66g2000hsc.googlegroups.com...
>I use VCS, not VCSi, but Synopsys added parameter dumping to VCS in
> one of the later releases, either 2006.06-SP1 or 2006.06-SP2 I think.
> What version of VCSi are you using?
>
> You can also ask at vcs_support@synopsys.com or ask Mentor if you can
> turn it off in Modelsim.
>
> Of course, this begs the question: why are you comparing waves files?
> Are you seeing different behavior from the two simulators or is it
> that you consider one to be golden and compare the other one to it? If
> the latter, you really should make your testbenches self-checking.
> It'll make your life much easier.
>
> -cb

"Dwayne Dilbeck" <ddilbeck@yahoo.com> writes:

> Thus a full VCD dump of the design in both simulators and comparison
> of the vcds was ordered.

You can't compare just using a lexical diff program. I would be
surprised if only the parameters where different from one vendor to
another. I would expect the order in which the net-names are mapped
would be different, one vendor might output a bus as individual
signals, the order the signals change within the same time-unit, etc.
to be different as well.

Hence you have to parse the VCD file, combine/split buses, and make
sure you compare the net names values and ignore their mapped VCD
names.

VCD can't represent enumerated types, interfaces, instances of
classes, assertions, etc. hence vendors might output this differently
in the VCD file. BTW, there is a clear need for an open effective dump
format which include all these types so that it could be useful for
SystemVerilog and VHDL as well.

I would say it would be better to focus on your self-checking
testbenches to catch these issues.

Petter

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On Aug 18, 4:13*pm, "Dwayne Dilbeck" <ddilb...@yahoo.com> wrote:
> VCS version: Y-2006-06-SP1

Then it must be SP2 where they added parameter dumping.


> I have my company vendor contact asking the same questions as well, but this
> group has a large amount of knowledge that may short cut the email bounce
> time.

True enough. You could always try both. There's always
verificationguild.com, too.


> We are seeing difference in simulator operations. Our IP passes the self
> checking test bench in one simnulator and fails in the other. The failure
> was tracked down and required a coding style change to work-around. This
> generated concern about any hidden coding style issues. *Thus a full VCD
> dump of the design in both simulators and comparison of the vcds was
> ordered.
> I, as the new guy, got the task.

Ok, now we get to the meat of it. My suggestions when this happens:

1) Run with optimizations off and debugging on. For VCS: don't use
+rad and do use -debug_all.
2) Run with race detection. VCS: +race

Race detection helps find questionable coding styles. Also, if you've
got a good linter, try that too, for the same reason. Your designers
are running some form of linting, right? And get them to actually read
all the synthesis warnings for a change, because they can also point
out questionable code.

Also, I expect it's worth adding assertions and/or checkers to help
narrow down the number of modules you have to check.

And if you suspect a bug, or a questionable interpretation of the LRM,
definitely work with the vendor. Of course, the LRM is sometimes
vague, I mean, allows different behavior in spots, such that both
simulators may technically be giving LRM-legal results, but that's
mostly a problem with unsafe code. I guarantee you there's a way to
write it that works correctly in both simulators. Finding it's the
hard part.

I know these situations can be a real pain. Best of luck.

-cb