Verilog simulation of placed/routed netlist using verilog XLThis is a discussion on Verilog simulation of placed/routed netlist using verilog XL within the verilog forums in Programming Languages category; Hi, I want to simulate the verilog netlist of placed and routed design obtained from Cadence SoC Encounter. I have the sdf file from SoC Encounter. I am using Verilog XL. I used the sdf_annotate command in my testbench as follows initial begin $sdf_annotate("./design.sdf",instance_name,,,,); end Is this the right way to do it? Thanks in advance. Regards, Ajay... | ||||||||
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08-25-2008, 12:06 PM
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 Verilog simulation of placed/routed netlist using verilog XL Hi, I want to simulate the verilog netlist of placed and routed design obtained from Cadence SoC Encounter. I have the sdf file from SoC Encounter. I am using Verilog XL. I used the sdf_annotate command in my testbench as follows initial begin $sdf_annotate("./design.sdf",instance_name,,,,); end Is this the right way to do it? Thanks in advance. Regards, Ajay  |
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