verilog adders (verilog optimization)

I had assumed Verilog would collapse constants, but I wonder if that
is
always trued/allowed?

If I have something like
reg [7:0] sig1, sig2, sig3;

always @ *
sig3 = 1 + 2 + 3 + sig1 + sig2 + 4;

There must be at least 2 adders. Is Verilog required to produce 3
adders?

The code can easily be collapsed to
sig3 = 6 + sig1 + sig2 + 4;

Verilog evaluates left to right, so this becomes
sig3 = ( (6 + sig1) + sig2) + 4;

This requires 3 adders. Is it legal for Verilog to compile the
original code to:
sig3 = 10 + sig1 + sig2;

Thoughts?

Thanks!

John Providenza

Most synthesis tools will take advantage of associative and
commutative properties of expressions in order to produce an optimal
implementation. If they don't, I don't use them very long.

Andy

On Aug 29, 7:03*am, Andy <jonesa...@comcast.net> wrote:
> Most synthesis tools will take advantage of associative and
> commutative properties of expressions in order to produce an optimal
> implementation. If they don't, I don't use them very long.
>
> Andy

For grins, I created a very simple test case and synthesized it
using the Xilinx XST synthesizer. Here's the code:

module test (
input clk,
input [7:0] a, b,

output reg [7:0] z
);



reg [7:0] a1, b1, z1;

always @(posedge clk)
begin
a1 <= a;
b1 <= b;
z <= z1;
end


always @ *
begin
z1 = 1 + 2 + 3 + a1 + b1 + 4;
end
endmodule


Guess what? 3 adders. If I reorder the arithmetic to be
z1 = 1 + 2 + 3 + 4 + a1 + b1;
then I get 2 adders.

John Providenza

On Aug 29, 7:38*am, jprovide...@yahoo.com wrote:
>
> For grins, I created a very simple test case and synthesized it
> using the Xilinx XST synthesizer. *Here's the code:
>
<snip>
> always @ *
> * * begin
> * * z1 = 1 + 2 + 3 + a1 + b1 + 4;
> * * end
> endmodule
>
> Guess what? *3 adders. * If I reorder the arithmetic to be
> * * z1 = 1 + 2 + 3 + *4 + a1 + b1;
> then I get 2 adders.
>
> John Providenza

Different synthesizers will produce different results. 20 years ago,
you might be hard pressed to find a Verilog synthesizer that wasn't
order-dependent but things are better now. The Xilinx XST has become
a respectable synthesizer but I still wouldn't call it a "world class"
synthesis engine. For a free tool, it's great.

A better synthesizer *might* produce repeatible results with minimal
logic. I don't think algebraic optimization is high on any
synthesizer's feature list, though, such that even exceptional logic
synthesizers might stumble on some simple arithmatic.

I'd personally love to see more work on algebraic optimization but I'm
not holding my breath.

- John_H

jprovidenza@yahoo.com wrote:

> Guess what? 3 adders. If I reorder the arithmetic to be
> z1 = 1 + 2 + 3 + 4 + a1 + b1;
> then I get 2 adders.

Try finishing the synthesis and compare LUTs and Flops.
Some reductions happen on the back-end.

-- Mike Treseler

On Aug 29, 9:54*am, Mike Treseler <mtrese...@gmail.com> wrote:
> jprovide...@yahoo.com wrote:
> > Guess what? *3 adders. * If I reorder the arithmetic to be
> > * * z1 = 1 + 2 + 3 + *4 + a1 + b1;
> > then I get 2 adders.
>
> Try finishing the synthesis and compare LUTs and Flops.
> Some reductions happen on the back-end.
>
> * * *-- Mike Treseler

Here's the XST synthesis data for the two cases. It sure looks to
me like there's extra logic.

I agree that XST is not well know as a state-of-the-art, super-duper,
terrific, knock-your-socks-off synthesizer, but it is a data point.

Code:
z1 = 1 + 2 + 3 + a1 + b1 + 4;
Cell Usage :
# BELS : 35
# GND : 1
# LUT1 : 1
# LUT2 : 7
# LUT3 : 1
# LUT4 : 7
# LUT5 : 1
# LUT6 : 1
# MUXCY : 7
# VCC : 1
# XORCY : 8
# FlipFlops/Latches : 24
# FD : 23
# FDR : 1

LUTS 18
XORCY 8
MUXCY 7



Code:
z1 = 1 + 2 + 3 + 4 + a1 + b1;
Cell Usage :
# BELS : 29
# GND : 1
# LUT1 : 1
# LUT2 : 6
# LUT4 : 6
# MUXCY : 7
# XORCY : 8
# FlipFlops/Latches : 24
# FD : 24

LUTS 13
XORCY 8
MUXCY 7


John Providenza

> Code:
> z1 = 1 + 2 + 3 + a1 + b1 + 4;
> Cell Usage :
> # BELS : 35
> # GND : 1
> # LUT1 : 1
> # LUT2 : 7
> # LUT3 : 1
> # LUT4 : 7
> # LUT5 : 1
> # LUT6 : 1
> # MUXCY : 7
> # VCC : 1
> # XORCY : 8
> # FlipFlops/Latches : 24
> # FD : 23
> # FDR : 1
>
> LUTS 18
> XORCY 8
> MUXCY 7
>
>
>
> Code:
> z1 = 1 + 2 + 3 + 4 + a1 + b1;
> Cell Usage :
> # BELS : 29
> # GND : 1
> # LUT1 : 1
> # LUT2 : 6
> # LUT4 : 6
> # MUXCY : 7
> # XORCY : 8
> # FlipFlops/Latches : 24
> # FD : 24
>
> LUTS 13
> XORCY 8
> MUXCY 7
>
>
> John Providenza

That's interesting. The fact that each design has 8 XORCYs leads me to
believe that there are only two adders, but I'm not sure why the LUT
count differs. It seems like there are only 8 LUTs needed--an 8-bit
adder (with truncated 8-bit output) should require only 4 LUTs and 4
XORCYs--so I don't know why there would be 13 and 18 LUTs used. Did you
look at the technology schematic?
-Kevin

jprovidenza@yahoo.com wrote:

> Here's the XST synthesis data for the two cases. It sure looks to
> me like there's extra logic.

Sure enough.
Thanks for trying it, and for reporting results.
Consider submitting the case with Xilinx
since you have all the data.

> I agree that XST is not well know as a state-of-the-art, super-duper,
> terrific, knock-your-socks-off synthesizer, but it is a data point.

Well, you have proven your point.
The synthesis front-end should be
smart enough to collect constants.

On the other hand, most designers
would do something like:
parameter sum = 1+2+3+4;

-- Mike Treseler

On Aug 29, 11:43*am, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
> > Code:
> > * * z1 = 1 + 2 + 3 + a1 + b1 + 4;
> > Cell Usage :
> > # BELS * * * * * * * * * * * * * * : 35
> > # * * *GND * * * * * * * * * * * * : 1
> > # * * *LUT1 * * * * * * * * * * * *: 1
> > # * * *LUT2 * * * * * * * * * * * *: 7
> > # * * *LUT3 * * * * * * * * * * * *: 1
> > # * * *LUT4 * * * * * * * * * * * *: 7
> > # * * *LUT5 * * * * * * * * * * * *: 1
> > # * * *LUT6 * * * * * * * * * * * *: 1
> > # * * *MUXCY * * * * * * * * * * * : 7
> > # * * *VCC * * * * * * * * * * * * : 1
> > # * * *XORCY * * * * * * * * * * * : 8
> > # FlipFlops/Latches * * * * * * * *: 24
> > # * * *FD * * * * * * * * * * * * *: 23
> > # * * *FDR * * * * * * * * * * * * : 1
>
> > LUTS * *18
> > XORCY * 8
> > MUXCY * 7
>
> > Code:
> > * * z1 = 1 + 2 + 3 + 4 + a1 + b1;
> > Cell Usage :
> > # BELS * * * * * * * * * * * * * * : 29
> > # * * *GND * * * * * * * * * * * * : 1
> > # * * *LUT1 * * * * * * * * * * * *: 1
> > # * * *LUT2 * * * * * * * * * * * *: 6
> > # * * *LUT4 * * * * * * * * * * * *: 6
> > # * * *MUXCY * * * * * * * * * * * : 7
> > # * * *XORCY * * * * * * * * * * * : 8
> > # FlipFlops/Latches * * * * * * * *: 24
> > # * * *FD * * * * * * * * * * * * *: 24
>
> > LUTS * *13
> > XORCY * 8
> > MUXCY * 7
>
> > John Providenza
>
> That's interesting. *The fact that each design has 8 XORCYs leads me to
> believe that there are only two adders, but I'm not sure why the LUT
> count differs. *It seems like there are only 8 LUTs needed--an 8-bit
> adder (with truncated 8-bit output) should require only 4 LUTs and 4
> XORCYs--so I don't know why there would be 13 and 18 LUTs used. *Did you
> look at the technology schematic?
> -Kevin

I did not look in any detail. At some point, each synthesizer will
"do its own thing",
so I don't really care about the very low level details. The
schematics showed
3 adders, 2 of them had constants as inputs.

I'm curious as to
a) does Verilog some how require this?
b) what do some other synthesizers do?

John Providenza

jprovidenza@yahoo.com wrote:

> I'm curious as to
> a) does Verilog some how require this?
I don't see how.
Both cases sim the same.

> b) what do some other synthesizers do?
Quartus does about the same thing.
3 then 2 adders at the rtl level for the same cases
and a few extra LUTs for the 3 counter case.

-- Mike Treseler