Custom Clock Signals

Hi,
I have a 50MHz clock and I'm trying to make something that uses a
clock signal at 21.48MHz.
The closest I can get the clock signal would be 20MHz with my ideas.
I'm not that crafty with Verilog yet, and am not sure of the
limitations etc. and am quite confused
about how to make custom signals to be frank.

50MHz*.4296 = 21.48MHz but i can't think of any way to perform
floating point math on a clock signal. Any suggestions?

Thanks

On Wed, 3 Sep 2008 06:14:14 -0700 (PDT), laserbeak43
<laserbeak43@gmail.com> wrote:

>Hi,
> I have a 50MHz clock and I'm trying to make something that uses a
>clock signal at 21.48MHz.
>The closest I can get the clock signal would be 20MHz with my ideas.
>I'm not that crafty with Verilog yet, and am not sure of the
>limitations etc. and am quite confused
>about how to make custom signals to be frank.
>
> 50MHz*.4296 = 21.48MHz but i can't think of any way to perform
>floating point math on a clock signal. Any suggestions?

It depends on how precise you need your 21.48MHz clock
to be, and it also depends on what sort of FPGA you have.

Many modern FPGAs have some kind of clock multiplier,
based on analog PLL technology of some kind, that will
give you frequency multiplication by M/N where M and N
are both integers within some limited range. There may
also be limits on the absolute value of clock output
frequency, so - for example - you might need to generate
42.96MHz and then divide by 2 in the conventional way.

Alternatively you can do some kind of pulse-skipping
thing so that you get an average frequency of 21.48MHz
by generating a pulse once for every two 50MHz clocks
but occasionally miss one pulse. Check out "direct
digital synthesis" or DDS for more information, or
ask again here - it's fairly easy to do. But of
course your clock will now have significant jitter
that may be unacceptable for your application.

Finally, it may be worth reviewing your actual
application to see if you can get the right behaviour
in a different way using the existing 50MHz clock.

Oh, and you could also get out your soldering iron and
replace the crystal :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Those are lots of options!!
I'm affraid i'm not good enough with an iron to replace a crystal
what i did find was something about DCM's in my starter kit's user
guide:
************************************
Alternatively, use
the FPGA’s Digital Clock Manager (DCM) to generate or synthesize other
frequencies from
the on-board 50 MHz oscillator.
**********************************
i'm searching the datasheet now. ok it pointed me to another
link...ahhh:
**********************************
Primarily, DCMs eliminate clock skew, thereby improving
system performance. Similarly, a DCM optionally phase shifts the clock
output to delay the
incoming clock by a fraction of the clock period. DCMs optionally
multiply or divide the
incoming clock frequency to synthesize a new clock frequency. The DCMs
integrate
directly with the FPGA’s global low-skew clock distribution network.
************************************
now all i gotta do is read on and learn how to do it!

Thanks for pointing me in the right direction


On Sep 3, 9:26*am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 3 Sep 2008 06:14:14 -0700 (PDT), laserbeak43
> It depends on how precise you need your 21.48MHz clock
> to be, and it also depends on what sort of FPGA you have.
>
> Many modern FPGAs have some kind of clock multiplier,
> based on analog PLL technology of some kind, that will
> give you frequency multiplication by M/N where M and N
> are both integers within some limited range. *There may
> also be limits on the absolute value of clock output
> frequency, so - for example - you might need to generate
> 42.96MHz and then divide by 2 in the conventional way.
>
> Alternatively you can do some kind of pulse-skipping
> thing so that you get an average frequency of 21.48MHz
> by generating a pulse once for every two 50MHz clocks
> but occasionally miss one pulse. *Check out "direct
> digital synthesis" or DDS for more information, or
> ask again here - it's fairly easy to do. *But of
> course your clock will now have significant jitter
> that may be unacceptable for your application.
>
> Finally, it may be worth reviewing your actual
> application to see if you can get the right behaviour
> in a different way using the existing 50MHz clock.
>
> Oh, and you could also get out your soldering iron and
> replace the crystal :-)
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

On Sep 3, 8:23*am, laserbeak43 <laserbea...@gmail.com> wrote:
> Those are lots of options!!
> I'm affraid i'm not good enough with an iron to replace a crystal
<snip>

Could you illustrate what you're trying to accomplish? What's the
purpose of the 21.48 MHz clock? Is it driving an analog interface?

Often clocks aren't needed to run at precision frequencies. FIFOs are
often used to "speed match" between different clocking domains. If a
clock is available elsewhere in your overall system (related to the
21.48MHz) you can feed clocks generated elsewhere back into the FPGA.

If you're working with a standard development board, there's a good
chance there's a socket for the/an oscillator. Check your board
documentation about clocking options. You might be a quick Digikey
purchase away from what you need for your requirements.

- John_H

On Wed, 3 Sep 2008 08:23:13 -0700 (PDT), laserbeak43 wrote:

> Alternatively, use the FPGA’s Digital Clock Manager
> (DCM) to generate or synthesize other frequencies
> from the on-board 50 MHz oscillator.

And then you will find that 50MHz*3/7 is rather close
to 21.48MHz - only about a quarter of a percent error.
Good enough? I couldn't find any other accessible
M/N values that were closer.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote in
news:i45vb4d1nn8sh5vimv03cg442pn7m18sje@4ax.com:

> On Wed, 3 Sep 2008 08:23:13 -0700 (PDT), laserbeak43 wrote:
>
>> Alternatively, use the FPGA’s Digital Clock Manager
>> (DCM) to generate or synthesize other frequencies
>> from the on-board 50 MHz oscillator.
>
> And then you will find that 50MHz*3/7 is rather close
> to 21.48MHz - only about a quarter of a percent error.
> Good enough? I couldn't find any other accessible
> M/N values that were closer.

The exact ratio is 537 / 1250, which can't be done using a DCM.
Nor can it be done with a conventional phase accumulator type
fractional-N divider.

It's simple enough to do with an FSM though.

Regards,
Allan

On Sep 4, 8:14*am, Allan Herriman <allanherri...@hotmail.com> wrote:
>
> The exact ratio is 537 / 1250, which can't be done using a DCM.
> Nor can it be done with a conventional phase accumulator type
> fractional-N divider.
>
> It's simple enough to do with an FSM though.
>
> Regards,
> Allan

A fractional N PLL can do this fine. An integer-N PLL can do this
fine with a 40kHz phase comparator frequency. No FSM will eliminate
the jitter. A DDS is better than an FSM given the number of states
involved.

You leave me very confused as to what your intent was with your
comments beyond the DCM.

If by "conventional phase accumulator type fractional-N divider" you
mean DDS, even that can provide an "exact" frequency using a non-2^n
modulus if the sub-ppb inaccuracy of a 32-bit DDS isn't sufficient.

On Sep 4, 4:59 pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Sep 4, 8:14 am, Allan Herriman <allanherri...@hotmail.com> wrote:
>
>
>
> > The exact ratio is 537 / 1250, which can't be done using a DCM.
> > Nor can it be done with a conventional phase accumulator type
> > fractional-N divider.
>
> > It's simple enough to do with an FSM though.
>
> > Regards,
> > Allan
>
> A fractional N PLL can do this fine. An integer-N PLL can do this
> fine with a 40kHz phase comparator frequency. No FSM will eliminate
> the jitter. A DDS is better than an FSM given the number of states
> involved.
>
> You leave me very confused as to what your intent was with your
> comments beyond the DCM.
>
> If by "conventional phase accumulator type fractional-N divider" you
> mean DDS, even that can provide an "exact" frequency using a non-2^n
> modulus if the sub-ppb inaccuracy of a 32-bit DDS isn't sufficient.

You may want to look at the code I posted here:

http://groups.google.com/group/comp....0d044579eba22a

(or Google for thread "Frequency Synthesis" in this newsgroup)

John_H <newsgroup@johnhandwork.com> wrote in news:b61ffd76-b12a-4a87-
984f-9e14d7033e59@r35g2000prm.googlegroups.com:

> On Sep 4, 8:14*am, Allan Herriman <allanherri...@hotmail.com> wrote:
>>
>> The exact ratio is 537 / 1250, which can't be done using a DCM.
>> Nor can it be done with a conventional phase accumulator type
>> fractional-N divider.
>>
>> It's simple enough to do with an FSM though.
>>
>> Regards,
>> Allan
>
> A fractional N PLL can do this fine. An integer-N PLL can do this
> fine with a 40kHz phase comparator frequency. No FSM will eliminate
> the jitter. A DDS is better than an FSM given the number of states
> involved.
>
> You leave me very confused as to what your intent was with your
> comments beyond the DCM.
>
> If by "conventional phase accumulator type fractional-N divider" you
> mean DDS, even that can provide an "exact" frequency using a non-2^n
> modulus if the sub-ppb inaccuracy of a 32-bit DDS isn't sufficient.

"[C]onventional phase accumulator type fractional-N divider[s]" have a
2^n modulus. I was merely pointing out that the exact frequency ratio
can't be achieved with a 2^n modulus.

BTW, a DDS is an FSM (but not all FSMs are DDSs), so I'm not sure about
your statement that a DDS can be better than an FSM.

Several years ago I wrote a fractional-N divider generator program. It's
still on the web:
http://fractional-divider.tripod.com/
It still works, too. The resultant code is not a DDS, but it does
produce an identical output.

However, I now use a more compact implementation (written directly in
HDL) for those rare cases when I need a fractional-N divider in a design.

Regards,
Allan