`default net_type noneThis is a discussion on `default net_type none within the verilog forums in Programming Languages category; I remember seeing that the directive `default net_type none was defined for Verilog2001 to allow undeclared variables to not revert to single wires but instead to flag an error such as a non- declared variable, a misspelling, or capitalization problems. I'm not finding this information in any of my conveniently accessible tool help or Verilog2001 references. Is this supported in most (or any) tools? My specific desires are mostly FPGA synthesis but the broader question still applies. Thanks, - John_H... | ||||||||
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#1
09-04-2008, 05:05 PM
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 `default net_type none I remember seeing that the directive `default net_type none was defined for Verilog2001 to allow undeclared variables to not revert to single wires but instead to flag an error such as a non- declared variable, a misspelling, or capitalization problems. I'm not finding this information in any of my conveniently accessible tool help or Verilog2001 references. Is this supported in most (or any) tools? My specific desires are mostly FPGA synthesis but the broader question still applies. Thanks, - John_H  |
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#2
09-04-2008, 05:17 PM
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| Re: `default net_type none On Sep 4, 5:05*pm, John_H <newsgr...@johnhandwork.com> wrote: > I remember seeing that the directive > > * * `default net_type none > > was defined for Verilog2001 to allow undeclared variables to not > revert to single wires but instead to flag an error such as a non- > declared variable, a misspelling, or capitalization problems. > > I'm not finding this information in any of my conveniently accessible > tool help or Verilog2001 references. > > Is this supported in most (or any) tools? *My specific desires are > mostly FPGA synthesis but the broader question still applies. > > Thanks, > - John_H Try: `default_nettype none Regards, Gabor |
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#3
09-04-2008, 09:56 PM
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| Re: `default net_type none gabor wrote: > On Sep 4, 5:05 pm, John_H <newsgr...@johnhandwork.com> wrote: >> I remember seeing that the directive >> >> `default net_type none >> >> was defined for Verilog2001 to allow undeclared variables to not >> revert to single wires but instead to flag an error such as a non- >> declared variable, a misspelling, or capitalization problems. >> >> I'm not finding this information in any of my conveniently accessible >> tool help or Verilog2001 references. >> >> Is this supported in most (or any) tools? My specific desires are >> mostly FPGA synthesis but the broader question still applies. >> >> Thanks, >> - John_H > > > Try: > > `default_nettype none > > Regards, > Gabor Thanks, Gabor. Suddenly there's 1130 Google hits. I feel much better now. - John_H |
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#4
09-05-2008, 08:22 AM
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| Re: `default net_type none On Sep 4, 9:56*pm, John_H <newsgr...@johnhandwork.com> wrote: > gabor wrote: > > On Sep 4, 5:05 pm, John_H <newsgr...@johnhandwork.com> wrote: > >> I remember seeing that the directive > > >> * * `default net_type none > > >> was defined for Verilog2001 to allow undeclared variables to not > >> revert to single wires but instead to flag an error such as a non- > >> declared variable, a misspelling, or capitalization problems. > > >> I'm not finding this information in any of my conveniently accessible > >> tool help or Verilog2001 references. > > >> Is this supported in most (or any) tools? *My specific desires are > >> mostly FPGA synthesis but the broader question still applies. > > >> Thanks, > >> - John_H > > > Try: > > > `default_nettype none > > > Regards, > > Gabor > > Thanks, Gabor. *Suddenly there's 1130 Google hits. *I feel much better now. > > - John_H No problem. I had to look it up myself, but it's much easier in the index of the Doulos Verilog Golden Reference Guide than on the web when you're not sure of the exact syntax. Regards, Gabor |
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