help needed on a complex macroThis is a discussion on help needed on a complex macro within the verilog forums in Programming Languages category; Hi, Can somebody explain what is m3 meant to be doing in this code? And before that, is it a valid verilog code? `define m1(a1,a2) a1 = a1 - a2; `define m2(a2,a3) (a2 * a3) `define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`" module mod; reg v1, v2, v3; always begin `m1(v1,v2); v3 = `m2(v1,v2); $display(`m3(v1)); end endmodule... | ||||||||
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#1
09-05-2008, 03:43 AM
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 help needed on a complex macro Hi, Can somebody explain what is m3 meant to be doing in this code? And before that, is it a valid verilog code? `define m1(a1,a2) a1 = a1 - a2; `define m2(a2,a3) (a2 * a3) `define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` \`"`" module mod; reg v1, v2, v3; always begin `m1(v1,v2); v3 = `m2(v1,v2); $display(`m3(v1)); end endmodule  |
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#2
09-05-2008, 02:43 PM
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| Re: help needed on a complex macro very_very_log wrote: > Hi, > > Can somebody explain what is m3 meant to be doing in this code? > And before that, is it a valid verilog code? > > `define m1(a1,a2) a1 = a1 - a2; > `define m2(a2,a3) (a2 * a3) > > `define m3(t) `" calling : `\`"m1(t)`\`"AND `\`m2(t)` > \`"`" > > > module mod; > > reg v1, v2, v3; > always begin > `m1(v1,v2); > v3 = `m2(v1,v2); > $display(`m3(v1)); > end > > endmodule > > This type of macro was introduced in Verilog 2001 (or 2005?). You really should avoid all precompiler macros if possible. The replacement works like this: `m1(v1,v2); becomes: v1 = v1 - v2; I don't really see the point of this here. -Kevin |
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