complex defines..

Hi all,
I have a define like
#define N_THREADS 4
I want to have another define depending on N_THREADS which should be
log (N_THREADS) to the base 2.
In the above example it becomes 2.Is there any such way...
Thanks,
Vittal

designer wrote:
> Hi all,
> I have a define like
> #define N_THREADS 4
> I want to have another define depending on N_THREADS which should be
> log (N_THREADS) to the base 2.
> In the above example it becomes 2.Is there any such way...
> Thanks,
> Vittal
You can sort of do this with defines, but it's messy and much better to
do it with parameters and constant functions, which most tools support
now. As in:

parameter N_THREADS=4;
parameter log2_N_THREADS=clog2(N_THREADS);

....

function clog2(...

-Kevin

"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:ga3p9j$puv2@cnn.xsj.xilinx.com...
> designer wrote:
>> Hi all,
>> I have a define like
>> #define N_THREADS 4
>> I want to have another define depending on N_THREADS which should be
>> log (N_THREADS) to the base 2.
>> In the above example it becomes 2.Is there any such way...
>> Thanks,
>> Vittal
> You can sort of do this with defines, but it's messy and much better to do
> it with parameters and constant functions, which most tools support now.
> As in:
>
> parameter N_THREADS=4;
> parameter log2_N_THREADS=clog2(N_THREADS);
>
> ...
>
> function clog2(...

Systemverilog-2008 will add a standard system-task $clog2(), which returns
log2() of its argument.
Unfortunately, no tools today support it yet. And you can bet industrywide
support is
years away...

function integer clog2;
input integer argument;
...
endfunction

On Sep 13, 12:19*am, "arko" <a...@winnet.com> wrote:
>
> Systemverilog-2008 will add a standard system-task $clog2(), which returns
> log2() of its argument.

This was actually added in Verilog-2005, along with the ability to use
this system function and certain others in constant expressions.

> Unfortunately, no tools today support it yet. *And you can bet industrywide
> support is
> years away...

I wouldn't be surprised. SystemVerilog has added an immense number of
features to be implemented, and the 2009 draft standard adds more.
This Verilog feature probably isn't very high priority for most
implementors.