File write operation

I am in the process of monitoring the activity on a data bus.
The data bus is 256 bit wide.
We have data placed on this data bus and the data stays in the bus for
only one clock cycle after which the next 256 bit data is placed on
the data bus.
I need to write this 256 bit data into a file in segments of 32
bits,One by one.

For example: if a_b_c_d_e_f_g_h (placed on the bus during first
clock cycle) and
i_j_k_l_m_n_o_p (placed on the bus during
second clock cycle)
are two 256 bit data words on the bus i want it to
be written into a file as follows:

a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p

I wanted to know file commands or system tasks to perform this
operation,as long as data is placed on the data bus and if at some
point the bus has no data on it,our file should have

..
..
..
o
p
x
x
x
x etc

Help me out with this.

On Mon, 8 Sep 2008 02:57:23 -0700 (PDT), Gokul wrote:

>I am in the process of monitoring the activity on a data bus.
>The data bus is 256 bit wide.
>We have data placed on this data bus and the data stays in the bus for
>only one clock cycle after which the next 256 bit data is placed on
>the data bus.
>I need to write this 256 bit data into a file in segments of 32
>bits,One by one.

I don't see why this is in any way difficult; it's just
standard file output.

First, open the output file and save the resulting file ID in
an integer variable:

integer id;
...
id = $fopen("my_output_file.txt");
if (id == 0) begin
// the file failed to open
$display("FATAL: Could not open output file");
$finish;
end

Now, every time you see a new 256-bit data value, write it
to the file as eight 32-bit values (in hex?):

reg [255:0] data_word;
integer lsb;
...
<<< get the data word from your hardware somehow>>>
...
for (lsb = 0; lsb < 256; lsb = lsb + 32)
$fdisplay(id, "%h", data_word[lsb +: 32]);

And finally, when you are all done, it's a good idea to
close the file:

$fclose(id);

I hope you can easily see how to parameterise this code
so that the slice size could be different from 32 bits...

If "data_word" is full of X bits, then you'll see Xs
appearing in the file - so there should be no need for
any special treatment for that.

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On Mon, 08 Sep 2008 11:05:44 +0100, Jonathan Bromley wrote:

> for (lsb = 0; lsb < 256; lsb = lsb + 32)
> $fdisplay(id, "%h", data_word[lsb +: 32]);

Sorry, this will display the least significant
32 bits first. You may wish to run the loop
the other way.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On Sep 8, 3:08 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Mon, 08 Sep 2008 11:05:44 +0100, Jonathan Bromley wrote:
> > for (lsb = 0; lsb < 256; lsb = lsb + 32)
> > $fdisplay(id, "%h", data_word[lsb +: 32]);
>
> Sorry, this will display the least significant
> 32 bits first. You may wish to run the loop
> the other way.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Thats not a problem....actually I want the LSBs to be displayed first.
Thank you so much for the assistance you provided...

Gokul

On Sep 8, 3:19 pm, Gokul <gokul.b...@gmail.com> wrote:
> On Sep 8, 3:08 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
> wrote:
>
>
>
> > On Mon, 08 Sep 2008 11:05:44 +0100, Jonathan Bromley wrote:
> > > for (lsb = 0; lsb < 256; lsb = lsb + 32)
> > > $fdisplay(id, "%h", data_word[lsb +: 32]);
>
> > Sorry, this will display the least significant
> > 32 bits first. You may wish to run the loop
> > the other way.
> > --
> > Jonathan Bromley, Consultant
>
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> > The contents of this message may contain personal views which
> > are not the views of Doulos Ltd., unless specifically stated.
>
> Thats not a problem....actually I want the LSBs to be displayed first.
> Thank you so much for the assistance you provided...
>
> Gokul

What about the clock control to the code???

Actually the code executes only once...The following is my code

integer n;
reg [255:0] data_word;
integer lsb;

always @ (posedge w_clk)
begin
n = $fopen("my_chip_outputs_client");
data_word = wrt_bus;
for (lsb = 0; lsb < 256; lsb = lsb + 32)
$fdisplay(n, "%b", data_word[lsb +: 32]);
$fclose(n);
end

The output file has got only one data word displayed in 8 segments of
32 bits each.

What possibly is the problem???

I thought that Since I ve given "$fclose(n); " ,It writes the first
data word and then closes the file.
So i removed that and compiled the code.Even then the file has got
only one data word and this time they are all Xs.

Help me get through this issue.

On Mon, 8 Sep 2008 03:37:07 -0700 (PDT), Gokul wrote:


>What about the clock control to the code???
>
>Actually the code executes only once...The following is my code
>
>integer n;
>reg [255:0] data_word;
>integer lsb;
>
>always @ (posedge w_clk)
>begin
>n = $fopen("my_chip_outputs_client");
>data_word = wrt_bus;
> for (lsb = 0; lsb < 256; lsb = lsb + 32)
> $fdisplay(n, "%b", data_word[lsb +: 32]);
>$fclose(n);
>end


????????

You're re-opening the file on every clock - so you will
see only the data for the very last clock; all others
will be overwritten.

Try this:

///////////////////////////////////////////////////
initial begin: FileMonitor

integer file_id;
reg [255:0] data_word;
integer lsb;

// Open the file, just once, at the start
file_id = $fopen("my_chip_outputs_client");

// Sample on every clock, but stop when you see
// the "all_finished" signal asserted
while (all_finished !== 1'b1) begin
@(posedge w_clk);
data_word = wrt_bus;
for (lsb = 0; lsb < 256; lsb = lsb + 32)
$fdisplay(n, "%b", data_word[lsb +: 32]);
end

$fclose(file_id);

end
////////////////////////////////////////////////////

OK, so this code assumes you have a signal "all_finished"
somewhere in your testbench, and the testbench drives this
signal to 1'b1 when it's finished its work. And of course
you need the clock to continue ticking for at least one
more cycle after that has happened. If you can't see an
easy way to do that, then simply replace this line:
while (all_finished !== 1'b1) begin
with
forever begin

and then your sim will stop just as it does now, without
closing the file; this should normally be OK, although
it's always safer to close the file properly if you can.

C'mon, it's only programming!!!!!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On Sep 8, 3:57 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Mon, 8 Sep 2008 03:37:07 -0700 (PDT), Gokul wrote:
> >What about the clock control to the code???
>
> >Actually the code executes only once...The following is my code
>
> >integer n;
> >reg [255:0] data_word;
> >integer lsb;
>
> >always @ (posedge w_clk)
> >begin
> >n = $fopen("my_chip_outputs_client");
> >data_word = wrt_bus;
> > for (lsb = 0; lsb < 256; lsb = lsb + 32)
> > $fdisplay(n, "%b", data_word[lsb +: 32]);
> >$fclose(n);
> >end
>
> ????????
>
> You're re-opening the file on every clock - so you will
> see only the data for the very last clock; all others
> will be overwritten.
>
> Try this:
>
> ///////////////////////////////////////////////////
> initial begin: FileMonitor
>
> integer file_id;
> reg [255:0] data_word;
> integer lsb;
>
> // Open the file, just once, at the start
> file_id = $fopen("my_chip_outputs_client");
>
> // Sample on every clock, but stop when you see
> // the "all_finished" signal asserted
> while (all_finished !== 1'b1) begin
> @(posedge w_clk);
> data_word = wrt_bus;
> for (lsb = 0; lsb < 256; lsb = lsb + 32)
> $fdisplay(n, "%b", data_word[lsb +: 32]);
> end
>
> $fclose(file_id);
>
> end
> ////////////////////////////////////////////////////
>
> OK, so this code assumes you have a signal "all_finished"
> somewhere in your testbench, and the testbench drives this
> signal to 1'b1 when it's finished its work. And of course
> you need the clock to continue ticking for at least one
> more cycle after that has happened. If you can't see an
> easy way to do that, then simply replace this line:
> while (all_finished !== 1'b1) begin
> with
> forever begin
>
> and then your sim will stop just as it does now, without
> closing the file; this should normally be OK, although
> it's always safer to close the file properly if you can.
>
> C'mon, it's only programming!!!!!
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Your enthusiastic replies are so inspiring...

Thanks