how to use `celldefine in verilog - verilog

On Oct 1, 11:56 am, zhurim...@gmail.com wrote:
> I'm just a beginner in Verilog. Yesterday, I read a design containing
> many `celldefine macros. For example,
>    `celldefine
>     module and21 (A1, B1, Y1);
>       input  A1, B1;
>      output Y1;
>      wire A1, B1, Y1;
>        and #(0.0, 0.0) and_cell (Y1, A, B);
>    `endcelldefine
>
> But I do not know much about this type of macro in Verilog. I
> searched
> on Internet for a while, and all what I got is just that this macro
> is
> used to mark a module as a cell module, and cell modules are used by
> PLI rountines. In coclusion, my current understanding on this is very
> shallow.
>
> Who experienced on this point, please teach me in more detail.
> I'm looking forward to any information from you.

Typically used for delay backannotation. Hence it is used in leaf cell
modeling.

Best regards,
ABC

zhurimail@gmail.com wrote:
> I'm just a beginner in Verilog. Yesterday, I read a design containing
> many `celldefine macros. For example,
> `celldefine
> module and21 (A1, B1, Y1);
> input A1, B1;
> output Y1;
> wire A1, B1, Y1;
> and #(0.0, 0.0) and_cell (Y1, A, B);
> `endcelldefine
>
>
> But I do not know much about this type of macro in Verilog. I
> searched
> on Internet for a while, and all what I got is just that this macro
> is
> used to mark a module as a cell module, and cell modules are used by
> PLI rountines. In coclusion, my current understanding on this is very
> shallow.
>
>
> Who experienced on this point, please teach me in more detail.
> I'm looking forward to any information from you.
>
>
>
If you are a beginner, I suggest forgetting about this macro. You will
probably never use anything like it; in fact, you may never need to
create timing-accurate models.
-Kevin

n Sep 30, 11:56 pm, zhurim...@gmail.com wrote:
> But I do not know much about this type of macro in Verilog. I
> searched
> on Internet for a while, and all what I got is just that this macro
> is
> used to mark a module as a cell module, and cell modules are used by
> PLI rountines. In coclusion, my current understanding on this is very
> shallow.


Also see your simulator manual to see what it does with `celldefine. I
think most of them can make use of it to automatically exclude library
cells from waves if you want. I've added `celldefine/endcelldefine to
some of my vendor library files for this reason. You can add
`celldefine at the top and `endcelldefine at the bottom of a file
containing lots of modules and they'll all be included in the
definition.

-cb

Hi,

I figured recently how to use `celldefine.

itz about declaring any design as a cell in verilog.

you can have either the library gates defined the way you showed or else you can also have your design as a cell.

experts please correct me if i am wrong...
below is an example with a library where 2 input and gate and or gate are used
module (a,b,y,z);
input a,b;
output y,z;
AN2 u1(a,b,y);
OR2 u2(a,b,z);
endmodule

`celldefine
module AN2 (A, B, Z);
input A, B;
output Z;
wire A, B, Z;
and #(0.0, 0.0) and_cell (Z, A, B);
endmodule
`endcelldefine

`celldefine
module OR2 (A,B,Z);
input A,B;
output Z;

wire A,B,Z;

or #(0.0, 0.0) or_cell (Z, A, B);

endmodule
`endcelldefine

thank you

In your case, the purpose of the original designer may be to limit PLI access to only those parts of the design marked as cells through "acc+=rw:%CELL" in VCS.