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		Rating Thread / Thread Starter	Last Post	Replies	Views
		Large test vectors	02-21-2007 05:14 PM	2	33
		Re: can I convert DPRAM to SPRAM?	02-21-2007 09:30 AM	4	54
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		using the 'include directive in verilog	02-21-2007 08:12 AM	2	694
		Combine Direct and Random vectors.	02-20-2007 09:04 PM	2	29
		Tri-state in RTL	02-20-2007 04:55 PM	8	73
		Combine Direct and Random vectors.	02-20-2007 03:44 PM	0	38
		Bad array access?	02-20-2007 03:29 PM	4	33
		Verilog: Simulating Transport Delays on Bidirectional Tristate Lines	02-20-2007 03:18 PM	2	131
		VCS and 4.1.1 compiler	02-20-2007 12:09 PM	2	85
		can I convert DPRAM to SPRAM?	02-20-2007 08:54 AM	0	35
		moving data from slower to faster clock domain	02-19-2007 08:29 PM	2	56
		problem in running simulating modelsim with simulink	02-19-2007 11:29 AM	0	49
		Specify block delays	02-19-2007 03:34 AM	0	57
		About hardware realization of specify blocks	02-19-2007 12:29 AM	0	37
		arguments of type inout in task	02-18-2007 12:28 PM	1	41
		Functional Coverage in Transaction Class (SV)	02-18-2007 06:08 AM	2	55
		Is there a reason why synthesis tools do not want to support hierarchical inferences	02-18-2007 04:42 AM	3	34
		When tool synthesize, does all logic convert into NAND gate?	02-17-2007 08:43 PM	2	94
		ENUM IN INTERFACE (SYS VLOG)	02-16-2007 09:13 PM	4	50
		Synopsys Leda rules for Verilog, what happened here?	02-15-2007 09:43 PM	0	71

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