How to do the shift bit operation in Array : vhdl

type B_Matrix is array (0 to 3) of std_logic_vector(15 downto 0);
signal MatrixB : B_Matrix :=(others =>(others=>'0'));

For example MatrixB has some values {"1000001010101010",
"1000001010111010",..........}

Now I want to get the first bit of MatrixB(2) to give variable ad like
that: ad := MatrixB(2, 15); It doesn't work. Sounds like I use the
wrong grammar. Does anybody know how to do that.

One more thing, Can I do the operation like :

d2Rkk is signed(17 downto 0):= (others=>'0');

d2Rkk (12 downto 0) :=signed(MatrixR(2, 15 downto 3));

It looks like if the variable is an array type, the element of the
array cannot do the normal operation as if they are independent ones. I
mean if MatrixR is std_logic_vector (15 downto 3), I can just do d2Rkk
(12 downto 0) :=signed(MatrixR( 15 downto 3)); Where I can find some
examples for array operations ? Thanks.

You index an array of arrays (slv is an array) as MatrixB(2)(15), not
(2,15).
Two-dimensional arrays are allowed in vhdl, but not synthesizable.
Arrays of arrays are allowed and synthesizable.

Andy

On Jan 24, 6:01 pm, "ZHIQUAN" <threeinchn...@gmail.com> wrote:
> type B_Matrix is array (0 to 3) of std_logic_vector(15 downto 0);
> signal MatrixB : B_Matrix :=(others =>(others=>'0'));
>
> For example MatrixB has some values {"1000001010101010",
> "1000001010111010",..........}
>
> Now I want to get the first bit of MatrixB(2) to give variable ad like
> that: ad := MatrixB(2, 15); It doesn't work. Sounds like I use the
> wrong grammar. Does anybody know how to do that.
>
> One more thing, Can I do the operation like :
>
> d2Rkk is signed(17 downto 0):= (others=>'0');
>
> d2Rkk (12 downto 0) :=signed(MatrixR(2, 15 downto 3));
>
> It looks like if the variable is an array type, the element of the
> array cannot do the normal operation as if they are independent ones. I
> mean if MatrixR is std_logic_vector (15 downto 3), I can just do d2Rkk
> (12 downto 0) :=signed(MatrixR( 15 downto 3)); Where I can find some
> examples for array operations ? Thanks.

"Andy" <jonesandy@comcast.net> wrote in message news:1169684529.308315.39460@s48g2000cws.googlegro ups.com...
....
> Two-dimensional arrays are allowed in vhdl, but not synthesizable.
> Arrays of arrays are allowed and synthesizable.

Multi-dimensional arrays in VHDL should be synthesizable.
Which tool did you find that does not support that ?

Rob

To be honest, I have not tried multidimensional arrays in a long time,
but synplicity did not support it, and I don't think they do now. Have
you found any that do?

I always use arrays of arrays (of arrays of...) . It gives you more
flexibility anyway.

matrix(2)(15 downto 8) <= a_byte;

matrix(3 downto 1) <= three_words;

matrix(3 downto 1)(15 downto 8) <= no_worky; -- three_bytes won't work

Those operations don't work with multidimensional arrays.

Besides, any multidimensional array can be represented as an array of
arrays (of...).

Andy

On Jan 24, 6:44 pm, "Rob Dekker" <r...@verific.com> wrote:
> "Andy" <jonesa...@comcast.net> wrote in messagenews:1169684529.308315.39460@s48g2000cws.go oglegroups.com......
>
> > Two-dimensional arrays are allowed in vhdl, but not synthesizable.
> > Arrays of arrays are allowed and synthesizable.Multi-dimensional arrays in VHDL should be synthesizable.
> Which tool did you find that does not support that ?
>
> Rob

So I cannot use it like MatrixA((17) <=MatrixB(1)(15) ？Error: parse
error, unexpected COLON

On 25 Jan, 16:23, "Andy" <jonesa...@comcast.net> wrote:
> To be honest, I have not tried multidimensional arrays in a long time,
> but synplicity did not support it, and I don't think they do now. Have
> you found any that do?
>
> I always use arrays of arrays (of arrays of...) . It gives you more
> flexibility anyway.
>
> matrix(2)(15 downto 8) <= a_byte;
>
> matrix(3 downto 1) <= three_words;
>
> matrix(3 downto 1)(15 downto 8) <= no_worky; -- three_bytes won't work
>
> Those operations don't work with multidimensional arrays.
>
> Besides, any multidimensional array can be represented as an array of
> arrays (of...).
>
> Andy
>
> On Jan 24, 6:44 pm, "Rob Dekker" <r...@verific.com> wrote:
>
>
>
> > "Andy" <jonesa...@comcast.net> wrote in messagenews:1169684529.308315.39460@s48g2000cws.go oglegroups.com......
>
> > > Two-dimensional arrays are allowed in vhdl, but not synthesizable.
> > > Arrays of arrays are allowed and synthesizable.Multi-dimensional arrays in VHDL should be synthesizable.
> > Which tool did you find that does not support that ?
>
> > Rob- Hide quoted text -- Show quoted text -

I cannot do like this: MatrixA(0 to 3)(17 downto 16)<= (others=>
MatrixB(0 to 3)(15));

MatrixA is array(integer range 0 to 3) of std_logic_vector (17 downto
0);
MatrixB is array(integer range 0 to 3) of std_logic_vector(15 downto
0);

Besides, I cannot use ":" to replace (0 to 3).

"Andy" <jonesandy@comcast.net> wrote in message news:1169742213.867087.261340@k78g2000cwa.googlegr oups.com...
> To be honest, I have not tried multidimensional arrays in a long time,
> but synplicity did not support it, and I don't think they do now. Have
> you found any that do?

Yes. Leonardo for sure. I wrote the synthesizer for it.
And Quartus II does, since is has a Verific front-end.
I would be surprised if Synplicity does not support it (at least now)

>
> I always use arrays of arrays (of arrays of...) . It gives you more
> flexibility anyway.
>
> matrix(2)(15 downto 8) <= a_byte;
>
> matrix(3 downto 1) <= three_words;
>
> matrix(3 downto 1)(15 downto 8) <= no_worky; -- three_bytes won't work
>
> Those operations don't work with multidimensional arrays.
>
> Besides, any multidimensional array can be represented as an array of
> arrays (of...).


You are right. Array-of-array has everything that 2-dim array has, and more.
I don't know why they even introduced the concept (of multi-dim arrays).
But is is there in the language, so tools should support it.

Rob

"ZHIQUAN" <threeinchnail@gmail.com> wrote in message news:1169761067.303374.143460@k78g2000cwa.googlegr oups.com...
>I cannot do like this: MatrixA(0 to 3)(17 downto 16)<= (others=>
> MatrixB(0 to 3)(15));
>
> MatrixA is array(integer range 0 to 3) of std_logic_vector (17 downto
> 0);
> MatrixB is array(integer range 0 to 3) of std_logic_vector(15 downto
> 0);

So you want to assign a few bits of each of the 4 elements of MatrixA
You cannot do that with the 0 to 3 slice as far as I know.
Please use a for-loop.

>
> Besides, I cannot use ":" to replace (0 to 3).
>

What made you think that the ":" does anything other than give you a syntax error ?

Rob Dekker wrote:

> Yes. Leonardo for sure. I wrote the synthesizer for it.

Congratulations.
That's the first synthesizer I used that
really covered VHDL-87.

> And Quartus II does, since is has a Verific front-end.

Interesting. Do you think the register duplication
issue we discussed in another thread could ever be fixed
in the front end, or will that always have to be
taken out by the fitter?

-- Mike Treseler

"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:51v0i8F1m8qf3U1@mid.individual.net...
> Rob Dekker wrote:
>
>> Yes. Leonardo for sure. I wrote the synthesizer for it.
>
> Congratulations.
> That's the first synthesizer I used that
> really covered VHDL-87.

Thanks !
The first implementation I did was quite terrible (back in '91-92), but after two rewrites it got pretty good..
Those were the days..

>
>> And Quartus II does, since is has a Verific front-end.
>
> Interesting. Do you think the register duplication
> issue we discussed in another thread could ever be fixed
> in the front end, or will that always have to be
> taken out by the fitter?

I am sorry Mike. Which thread was that ?

>
> -- Mike Treseler
>
>