Datapath design problem? - vhdl

On 26 Jan., 07:37, "Shenli" <zhushe...@gmail.com> wrote:
> Hi all,
>
> I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
>
> It says "The most important technique to improve the performance of a
> datapath is to avoid expensive carry-propagations and to make use of
> redundant representations instead (like carry-save or partial-product)
> wherever possible."
>
> 1. Is there any article talk about what's "carry-propagation" and how
> to avoid use it?

When adding two words, you might get a carry at a bit position
affecting all "higher" bits of the result.
The task of spreading this carry to all other bits is the propagation.
Start with the following site:
http://en.wikipedia.org/wiki/Adder_%28electronics%29
It yould be good to use google to answer questions the article may
left.

> 2. What's "redundant representations" mean?

Redundant in this case means you double your logic to calculate one
block with carry = 0 and one with carry = 1 and select the result
depending on the real carry. This is useful, if you use blocks of 4 to
8 bits for adding two 64 bit integer as the longest path reduces from
64 full adder to eg. 8 bit full adder plus something like 8 mux to
select the correct result.

If you use an FPGA, you wil detect, that you have fast carry chains
that outperfom most other adder solutions, so this guide is wrong for a
lot of designs.

bye Thomas

Shenli wrote:
> Hi all,
>
> I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys.
>
> It says "The most important technique to improve the performance of a
> datapath is to avoid expensive carry-propagations and to make use of
> redundant representations instead (like carry-save or partial-product)
> wherever possible."
>
> 1. Is there any article talk about what's "carry-propagation" and how
> to avoid use it?
> 2. What's "redundant representations" mean?
>
> Please recommend some readings about it, thanks in advance!
>
> Best regards,
> Davy
>

That really is targeted to ASIC implementations. The performance hit
for carry propagation in FPGAs that have a "fast carry chain" is
mitigated by the much faster carry propagation on these special
dedicated circuits. With that in mind, if you are designing on an FPGA
with fast carry logic, then this admonishment doesn't apply.

Redundant representations refer to alternative number system
representations that avoid the propagation of a carry signal across the
width of a data word as a result of arithmetic operations. They are
not,however, without their own hardships.

Hello Everyone,

May be I am in wrong thread, but have a question about datapath:

Is it actually possible to extract data path components such as (adder, PC, registers, ...) from a given instruction set? As I understood by using ADL (Architecture description language) such as EXPRESSION, LISA …, where you can define all instructions, it should be easily done.
Is it right, does anyone have an experience in this area?

Thanks