help for "sll" shift left logical - vhdl

This is a discussion on help for "sll" shift left logical - vhdl ; hi every body i hope that someone help into this problem: into my entity i have as input : x : in STD_LOGIC_VECTOR(9 downto 0); and as an output: y ut STD_LOGIC_VECTOR(19 downto 0); my problem is in my architecture ...

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help for "sll" shift left logical

  1. Default help for "sll" shift left logical

    hi every body
    i hope that someone help into this problem:
    into my entity i have as input :
    x : in STD_LOGIC_VECTOR(9 downto 0);
    and as an output:
    yut STD_LOGIC_VECTOR(19 downto 0);

    my problem is in my architecture :
    y <= x sll 9 ;

    i get an error :"sll can not have such operands in this context."
    and i did try an example from xilinx and it isnt work too :
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity lshift is
    port(DI : in std_logic_vector(7 downto 0);
    sel : in std_logic_vector(1 downto 0);
    SO : out std_logic_vector(7 downto 0));
    end lshift;
    architecture archi of lshift is
    begin
    with sel select
    SO <= DI when "00",
    DI sll 1 when "01",
    DI sll 2 when others;
    end archi;
    --------------------------------------------------------------------------------
    i have the same error .
    Can you help me please and thank you


  2. Default Re: help for "sll" shift left logical

    On 6 Mar, 11:28, "VHDL_HELP" <abai...@gmail.com> wrote:
    > hi every body
    > i hope that someone help into this problem:
    > into my entity i have as input :
    > x : in STD_LOGIC_VECTOR(9 downto 0);
    > and as an output:
    > yut STD_LOGIC_VECTOR(19 downto 0);
    >
    > my problem is in my architecture :
    > y <= x sll 9 ;
    >
    > i get an error :"sll can not have such operands in this context."
    > and i did try an example from xilinx and it isnt work too :
    > ----------------------------------------------------------------------------------
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity lshift is
    > port(DI : in std_logic_vector(7 downto 0);
    > sel : in std_logic_vector(1 downto 0);
    > SO : out std_logic_vector(7 downto 0));
    > end lshift;
    > architecture archi of lshift is
    > begin
    > with sel select
    > SO <= DI when "00",
    > DI sll 1 when "01",
    > DI sll 2 when others;
    > end archi;
    > --------------------------------------------------------------------------------
    > i have the same error .
    > Can you help me please and thank you


    from what i remember sll is a bit_vector operation, thus doesnt exist
    within the std_logic_1164 library so is not part of std_logic_vector,
    just change your code to use bitvectors instead.


  3. Default Re: help for "sll" shift left logical

    VHDL_HELP wrote:

    > y <= x sll 9 ;
    > i get an error :"sll can not have such operands in this context."


    http://groups.google.com/groups/sear...c_std+unsigned

    -- Mike Treseler

  4. Default Re: help for "sll" shift left logical

    On 6 mar, 12:55, Mike Treseler <mike_trese...@comcast.net> wrote:
    > VHDL_HELP wrote:
    > > y <= x sll 9 ;
    > > i get an error :"sll can not have such operands in this context."

    >
    > http://groups.google.com/groups/sear...c_std+unsigned
    >
    > -- Mike Treseler


    Why not
    x <= x(2 downto 0) & '0' ?
    -weber


  5. Default Re: help for "sll" shift left logical

    Convert to unsigned or integer and muliply by 2**n, where n is the
    number of bit positions to shift. Synthesis will not use a multiplier
    for static powers of two.

    Andy

    On Mar 6, 5:28 am, "VHDL_HELP" <abai...@gmail.com> wrote:
    > hi every body
    > i hope that someone help into this problem:
    > into my entity i have as input :
    > x : in STD_LOGIC_VECTOR(9 downto 0);
    > and as an output:
    > yut STD_LOGIC_VECTOR(19 downto 0);
    >
    > my problem is in my architecture :
    > y <= x sll 9 ;
    >
    > i get an error :"sll can not have such operands in this context."
    > and i did try an example from xilinx and it isnt work too :
    > ----------------------------------------------------------------------------------
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > entity lshift is
    > port(DI : in std_logic_vector(7 downto 0);
    > sel : in std_logic_vector(1 downto 0);
    > SO : out std_logic_vector(7 downto 0));
    > end lshift;
    > architecture archi of lshift is
    > begin
    > with sel select
    > SO <= DI when "00",
    > DI sll 1 when "01",
    > DI sll 2 when others;
    > end archi;
    > --------------------------------------------------------------------------------
    > i have the same error .
    > Can you help me please and thank you




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