[how to make?] mux 1x1 128 bits + for generate - vhdl

This is a discussion on [how to make?] mux 1x1 128 bits + for generate - vhdl ; Hi. In first place, sorry for my bad English. I have a problem/question: I constructed one mux 1x1 with 128 bits input and 16 bits output: ------------------------------------------------------------------------------- -- -- Project : Multiplexer 1x1 -- File name : mux_1x1_128x16bits.vhd -- Title ...

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[how to make?] mux 1x1 128 bits + for generate

  1. Default [how to make?] mux 1x1 128 bits + for generate

    Hi.

    In first place, sorry for my bad English. I have a problem/question:
    I constructed one mux 1x1 with 128 bits input and 16 bits output:

    -------------------------------------------------------------------------------
    --
    -- Project : Multiplexer 1x1
    -- File name : mux_1x1_128x16bits.vhd
    -- Title : Multiplexer 1 input x 1 output
    -- Description : Multiplexer 1 input x 1 output 128x16 bits.
    --

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;

    ENTITY mux_1x1_128x16bits IS
    GENERIC
    (
    bits : integer:= 16;
    word : integer:= 8
    );
    PORT
    (
    I : IN STD_LOGIC_VECTOR(bits * word - 1 DOWNTO bits - bits);
    -- Q(7)Q(6)Q(5)Q(4)Q(3)Q(2)Q(1)Q(0)
    selector : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    O : OUT STD_LOGIC_VECTOR(bits - 1 DOWNTO bits - bits)
    );
    END mux_1x1_128x16bits;

    ARCHITECTURE a OF mux_1x1_128x16bitss IS
    BEGIN

    mux:
    FOR x IN 0 TO word - 1 GENERATE

    IF (selector = "???") THEN
    O <= I(((x * bits) + 15) DOWNTO (x * bits));
    END IF;

    END GENERATE;

    END a;

    It has a true-table below:

    Selector 000 = Q0
    Selector 001 = Q1
    Selector 010 = Q2
    Selector 011 = Q3
    Selector 100 = Q4
    Selector 101 = Q5
    Selector 110 = Q6
    Selector 111 = Q7

    in Q0 state the output is O <= I(15 DOWNTO 0)
    in Q1 state the output is O <= I(31 DOWNTO 16)
    in Q2 state the output is O <= I(47 DOWNTO 32)
    in Q3 state the output is O <= I(63 DOWNTO 48)
    in Q4 state the output is O <= I(79 DOWNTO 64)
    in Q5 state the output is O <= I(95 DOWNTO 80)
    in Q6 state the output is O <= I(111 DOWNTO 96)
    in Q7 state the output is O <= I(127 DOWNTO 112)

    My question is:

    Now I constructed a mux to 128 bits, but I will have many others mux,
    with different values in input OR output. I need a function to
    calculate automatically a "???".

    IF (selector = "???") THEN

    How to make this?

    I do not know if I was enough clearly

    Grateful

    Conrado Jr.


  2. Default Re: [how to make?] mux 1x1 128 bits + for generate

    conradojr wrote:
    > Hi.
    >
    > In first place, sorry for my bad English. I have a problem/question:
    > I constructed one mux 1x1 with 128 bits input and 16 bits output:
    >
    > -------------------------------------------------------------------------------
    > --
    > -- Project : Multiplexer 1x1
    > -- File name : mux_1x1_128x16bits.vhd
    > -- Title : Multiplexer 1 input x 1 output
    > -- Description : Multiplexer 1 input x 1 output 128x16 bits.
    > --
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.ALL;
    >
    > ENTITY mux_1x1_128x16bits IS
    > GENERIC
    > (
    > bits : integer:= 16;
    > word : integer:= 8
    > );
    > PORT
    > (
    > I : IN STD_LOGIC_VECTOR(bits * word - 1 DOWNTO bits - bits);
    > -- Q(7)Q(6)Q(5)Q(4)Q(3)Q(2)Q(1)Q(0)
    > selector : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    > O : OUT STD_LOGIC_VECTOR(bits - 1 DOWNTO bits - bits)
    > );
    > END mux_1x1_128x16bits;
    >
    > ARCHITECTURE a OF mux_1x1_128x16bitss IS
    > BEGIN
    >
    > mux:
    > FOR x IN 0 TO word - 1 GENERATE
    >
    > IF (selector = "???") THEN
    > O <= I(((x * bits) + 15) DOWNTO (x * bits));
    > END IF;
    >
    > END GENERATE;
    >
    > END a;
    >
    > It has a true-table below:
    >
    > Selector 000 = Q0
    > Selector 001 = Q1
    > Selector 010 = Q2
    > Selector 011 = Q3
    > Selector 100 = Q4
    > Selector 101 = Q5
    > Selector 110 = Q6
    > Selector 111 = Q7
    >
    > in Q0 state the output is O <= I(15 DOWNTO 0)
    > in Q1 state the output is O <= I(31 DOWNTO 16)
    > in Q2 state the output is O <= I(47 DOWNTO 32)
    > in Q3 state the output is O <= I(63 DOWNTO 48)
    > in Q4 state the output is O <= I(79 DOWNTO 64)
    > in Q5 state the output is O <= I(95 DOWNTO 80)
    > in Q6 state the output is O <= I(111 DOWNTO 96)
    > in Q7 state the output is O <= I(127 DOWNTO 112)
    >
    > My question is:
    >
    > Now I constructed a mux to 128 bits, but I will have many others mux,
    > with different values in input OR output. I need a function to
    > calculate automatically a "???".
    >
    > IF (selector = "???") THEN
    >
    > How to make this?
    >
    > I do not know if I was enough clearly
    >
    > Grateful
    >
    > Conrado Jr.
    >

    Hi Conrado Jr.

    Here is my suggestion for a generic mux:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity mux is
    generic ( data_width : in positive := 16;
    num_of_chans : in positive range 1 to 256 := 6);
    port ( data_in : in std_logic_vector((data_width*num_of_chans)-1
    downto 0);
    sel : in std_logic_vector(7 downto 0);
    data_out : out std_logic_vector(data_width-1 downto 0));
    end entity mux;

    architecture behave of mux is
    begin
    p_comb_mux : process (data_in, sel) is
    variable sel_int : integer;
    begin
    sel_int := to_integer(unsigned(sel));
    assert (((sel_int+1)*data_width)-1) <= data_in'left
    report "Value of select signal is out of range."
    severity error;
    data_out <= data_in((((sel_int+1)*data_width)-1) downto
    sel_int*data_width);
    end process p_comb_mux;
    end architecture behave;

    (You will have to fix some linebreaks to use it)

  3. Default Re: mux 1x1 128 bits + for generate

    A synthesizable architecture for the above entity is as follows:

    ARCHITECTURE rtl OF mux IS
    BEGIN
    main : PROCESS (data_in, sel) IS
    BEGIN
    data_out <= (OTHERS => '0'); -- default to avoid latch
    FOR i IN 0 TO num_of_chans - 1 LOOP
    IF i = to_integer(unsigned(sel)) THEN
    data_out <= data_in((i+1)*data_width-1 DOWNTO i*data_width);
    EXIT;
    END IF;
    END LOOP;
    END PROCESS main;
    END rtl;

    Note that all pointer arithmetic is done on the loop index, which is
    static when unrolled in synthesis, and thus is not subject to
    computation in hardware.

    Note also the default assignment prior to the loop to prevent latches
    in this combinatorial process. If you don't care what happens when SEL
    is out of range, then assign to '-' instead of '0';

    Andy




  4. Default Re: mux 1x1 128 bits + for generate

    Andy wrote:
    > A synthesizable architecture for the above entity is as follows:
    >
    > ARCHITECTURE rtl OF mux IS
    > BEGIN
    > main : PROCESS (data_in, sel) IS
    > BEGIN
    > data_out <= (OTHERS => '0'); -- default to avoid latch
    > FOR i IN 0 TO num_of_chans - 1 LOOP
    > IF i = to_integer(unsigned(sel)) THEN
    > data_out <= data_in((i+1)*data_width-1 DOWNTO i*data_width);
    > EXIT;
    > END IF;
    > END LOOP;
    > END PROCESS main;
    > END rtl;
    >
    > Note that all pointer arithmetic is done on the loop index, which is
    > static when unrolled in synthesis, and thus is not subject to
    > computation in hardware.
    >
    > Note also the default assignment prior to the loop to prevent latches
    > in this combinatorial process. If you don't care what happens when SEL
    > is out of range, then assign to '-' instead of '0';
    >
    > Andy
    >
    >
    >

    Yes, that one would be a better choice

    Forgetting default values is a bad habit of mine

    mamu

  5. Default Re: mux 1x1 128 bits + for generate

    On Apr 19, 9:26 pm, conradojr <conrad...@gmail.com> wrote:
    > Hi.
    >
    > In first place, sorry for my bad English. I have a problem/question:
    > I constructed one mux 1x1 with 128 bits input and 16 bits output:
    >
    > -------------------------------------------------------------------------------
    > --
    > -- Project : Multiplexer 1x1
    > -- File name : mux_1x1_128x16bits.vhd
    > -- Title : Multiplexer 1 input x 1 output
    > -- Description : Multiplexer 1 input x 1 output 128x16 bits.
    > --
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.ALL;
    >
    > ENTITY mux_1x1_128x16bits IS
    > GENERIC
    > (
    > bits : integer:= 16;
    > word : integer:= 8
    > );
    > PORT
    > (
    > I : IN STD_LOGIC_VECTOR(bits * word - 1 DOWNTO bits - bits);
    > -- Q(7)Q(6)Q(5)Q(4)Q(3)Q(2)Q(1)Q(0)
    > selector : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    > O : OUT STD_LOGIC_VECTOR(bits - 1 DOWNTO bits - bits)
    > );
    > END mux_1x1_128x16bits;
    >
    > ARCHITECTURE a OF mux_1x1_128x16bitss IS
    > BEGIN
    >
    > mux:
    > FOR x IN 0 TO word - 1 GENERATE
    >
    > IF (selector = "???") THEN
    > O <= I(((x * bits) + 15) DOWNTO (x * bits));
    > END IF;
    >
    > END GENERATE;
    >
    > END a;
    >
    > It has a true-table below:
    >
    > Selector 000 = Q0
    > Selector 001 = Q1
    > Selector 010 = Q2
    > Selector 011 = Q3
    > Selector 100 = Q4
    > Selector 101 = Q5
    > Selector 110 = Q6
    > Selector 111 = Q7
    >
    > in Q0 state the output is O <= I(15 DOWNTO 0)
    > in Q1 state the output is O <= I(31 DOWNTO 16)
    > in Q2 state the output is O <= I(47 DOWNTO 32)
    > in Q3 state the output is O <= I(63 DOWNTO 48)
    > in Q4 state the output is O <= I(79 DOWNTO 64)
    > in Q5 state the output is O <= I(95 DOWNTO 80)
    > in Q6 state the output is O <= I(111 DOWNTO 96)
    > in Q7 state the output is O <= I(127 DOWNTO 112)
    >
    > My question is:
    >
    > Now I constructed a mux to 128 bits, but I will have many others mux,
    > with different values in input OR output. I need a function to
    > calculate automatically a "???".
    >
    > IF (selector = "???") THEN
    >
    > How to make this?
    >
    > I do not know if I was enough clearly
    >
    > Grateful
    >
    > Conrado Jr.


    i posted this code before !!

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;
    --
    ENTITY Mux IS
    GENERIC(
    d_width : natural := 16;
    a_width : natural := 3
    );
    PORT(
    data_in : IN std_logic_vector(d_width*2**a_width-1 DOWNTO 0);
    sel : IN std_logic_vector(a_width-1 DOWNTO 0);
    data_out : OUT std_logic_vector(d_width-1 DOWNTO 0)
    );
    END Mux;
    --
    ARCHITECTURE Arch OF Mux IS
    BEGIN
    PROCESS(data_in,sel)
    BEGIN
    data_out <= (OTHERS => 'Z');
    FOR i IN 0 TO 2**a_width-1 LOOP
    IF ( sel = std_logic_vector(to_unsigned(i,a_width)) ) THEN
    data_out <= data_in((i+1)*d_width-1 DOWNTO i*d_width);
    END IF;
    END LOOP;
    END PROCESS;
    END Arch;

    Ahmed Samieh


  6. Default Re: mux 1x1 128 bits + for generate

    On Apr 26, 2:52 am, Ahmed Samieh <Asm4...@gmail.com> wrote:
    > On Apr 19, 9:26 pm, conradojr <conrad...@gmail.com> wrote:
    >
    >
    >
    > > Hi.

    >
    > > In first place, sorry for my bad English. I have a problem/question:
    > > I constructed one mux 1x1 with 128 bits input and 16 bits output:

    >
    > > -------------------------------------------------------------------------------
    > > --
    > > -- Project : Multiplexer 1x1
    > > -- File name : mux_1x1_128x16bits.vhd
    > > -- Title : Multiplexer 1 input x 1 output
    > > -- Description : Multiplexer 1 input x 1 output 128x16 bits.
    > > --

    >
    > > LIBRARY ieee;
    > > USE ieee.std_logic_1164.ALL;

    >
    > > ENTITY mux_1x1_128x16bits IS
    > > GENERIC
    > > (
    > > bits : integer:= 16;
    > > word : integer:= 8
    > > );
    > > PORT
    > > (
    > > I : IN STD_LOGIC_VECTOR(bits * word - 1 DOWNTO bits - bits);
    > > -- Q(7)Q(6)Q(5)Q(4)Q(3)Q(2)Q(1)Q(0)
    > > selector : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    > > O : OUT STD_LOGIC_VECTOR(bits - 1 DOWNTO bits - bits)
    > > );
    > > END mux_1x1_128x16bits;

    >
    > > ARCHITECTURE a OF mux_1x1_128x16bitss IS
    > > BEGIN

    >
    > > mux:
    > > FOR x IN 0 TO word - 1 GENERATE

    >
    > > IF (selector = "???") THEN
    > > O <= I(((x * bits) + 15) DOWNTO (x * bits));
    > > END IF;

    >
    > > END GENERATE;

    >
    > > END a;

    >
    > > It has a true-table below:

    >
    > > Selector 000 = Q0
    > > Selector 001 = Q1
    > > Selector 010 = Q2
    > > Selector 011 = Q3
    > > Selector 100 = Q4
    > > Selector 101 = Q5
    > > Selector 110 = Q6
    > > Selector 111 = Q7

    >
    > > in Q0 state the output is O <= I(15 DOWNTO 0)
    > > in Q1 state the output is O <= I(31 DOWNTO 16)
    > > in Q2 state the output is O <= I(47 DOWNTO 32)
    > > in Q3 state the output is O <= I(63 DOWNTO 48)
    > > in Q4 state the output is O <= I(79 DOWNTO 64)
    > > in Q5 state the output is O <= I(95 DOWNTO 80)
    > > in Q6 state the output is O <= I(111 DOWNTO 96)
    > > in Q7 state the output is O <= I(127 DOWNTO 112)

    >
    > > My question is:

    >
    > > Now I constructed a mux to 128 bits, but I will have many others mux,
    > > with different values in input OR output. I need a function to
    > > calculate automatically a "???".

    >
    > > IF (selector = "???") THEN

    >
    > > How to make this?

    >
    > > I do not know if I was enough clearly

    >
    > > Grateful

    >
    > > Conrado Jr.

    >
    > i posted this code before !!
    >
    > LIBRARY ieee;
    > USE ieee.std_logic_1164.all;
    > USE ieee.numeric_std.all;
    > --
    > ENTITY Mux IS
    > GENERIC(
    > d_width : natural := 16;
    > a_width : natural := 3
    > );
    > PORT(
    > data_in : IN std_logic_vector(d_width*2**a_width-1 DOWNTO 0);
    > sel : IN std_logic_vector(a_width-1 DOWNTO 0);
    > data_out : OUT std_logic_vector(d_width-1 DOWNTO 0)
    > );
    > END Mux;
    > --
    > ARCHITECTURE Arch OF Mux IS
    > BEGIN
    > PROCESS(data_in,sel)
    > BEGIN
    > data_out <= (OTHERS => 'Z');
    > FOR i IN 0 TO 2**a_width-1 LOOP
    > IF ( sel = std_logic_vector(to_unsigned(i,a_width)) ) THEN
    > data_out <= data_in((i+1)*d_width-1 DOWNTO i*d_width);
    > END IF;
    > END LOOP;
    > END PROCESS;
    > END Arch;
    >
    > Ahmed Samieh


    Ahmed,

    What you have posted creates a tri-state driver on the output of a
    mux, which is a different function from what was posted previously.

    It is also a common mistake made when users try to create a tri-state
    bus with multiple tri-state buffers (instead of a mux), though I
    cannot tell what your intentions were.

    To create a tri-state bus (with multiple tri-state buffers), you must
    create separate vhdl drivers for the signal, each one either driving
    its own value or 'Z', as appropriate. This means multiple processes
    (implied or explicit). For an arbitrary number of buffers, the only
    solution involves the use of a generate statement.

    Andy


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