shift/rotate operator for std_logic_vector - vhdl

This is a discussion on shift/rotate operator for std_logic_vector - vhdl ; I mean operators like ror, rol, sla, sra, srl, sll. Are they overloaded for std_logic_vector type in any 'standard' package? I use Altera Quartus 6.1, and I recieive a message: "Error (10327): VHDL error at vector_selector.vhd(191): can't determine definition of ...

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shift/rotate operator for std_logic_vector

  1. Default shift/rotate operator for std_logic_vector

    I mean operators like ror, rol, sla, sra, srl, sll.
    Are they overloaded for std_logic_vector type in any 'standard' package?

    I use Altera Quartus 6.1, and I recieive a message:
    "Error (10327): VHDL error at vector_selector.vhd(191): can't determine
    definition of operator ""srl"" -- found 0 possible definitions".

    MR

  2. Default Re: shift/rotate operator for std_logic_vector

    Marteno Rodia wrote:
    > I mean operators like ror, rol, sla, sra, srl, sll.
    > Are they overloaded for std_logic_vector type in any 'standard' package?


    Let's have a look at the source:
    http://www.eda.org/rassp/vhdl/models...umeric_std.vhd

    The shifts work differently for
    signed vs unsigned. Thats also why sla and sra are
    not defined. The vector type covers it.

    But it's not hard to cast out the
    numeric interpretation when the math is done:

    my_slv <= std_logic_vector(my_uns_vec srl 1);

    > I use Altera Quartus 6.1, and I recieive a message:
    > "Error (10327): VHDL error at vector_selector.vhd(191): can't determine
    > definition of operator ""srl"" -- found 0 possible definitions".


    That the right answer. There is no srl defined for std_logic_vector.

    -- Mike Treseler

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