asynchronous design basic - vhdl

On Sun, 14 Oct 2007 02:11:06 -0700, airol <hairoljb@gmail.com> wrote:

>I'm a beginner and would like to learn asynchronous design.

Looks like you're about 35 miles too far west :-)
A brief trip along the cyber-M62 will get you to

http://intranet.cs.man.ac.uk/apt/pro...essors/amulet/

which should start you off on various lines of enquiry.
Don't start arguing about football, though.

Also, try googling for "Muller C-element", and also
look at Handshake Solutions products.

Sometimes, asynch design is known as "self timed logic".
That may help.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
> Looks like you're about 35 miles too far west :-)
> A brief trip along the cyber-M62 will get you to
>
> http://intranet.cs.man.ac.uk/apt/pro...essors/amulet/

Just to add to that there is also the ARM996HS, a fully 5TE ISA
compatible embedded core

http://www.arm.com/products/CPUs/ARM996HS.html

Regards
Marcus

--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]

(seen on http://www.veripool.com/verilog-mode_news.html)

On Oct 16, 12:25 pm, Marcus Harnisch <marcus.harni...@gmx.net> wrote:
> Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> writes:
> > Looks like you're about 35 miles too far west :-)
> > A brief trip along the cyber-M62 will get you to
>
> >http://intranet.cs.man.ac.uk/apt/pro...essors/amulet/
>
> Just to add to that there is also the ARM996HS, a fully 5TE ISA
> compatible embedded core
>
> http://www.arm.com/products/CPUs/ARM996HS.html
>
> Regards
> Marcus
>
> --
> note that "property" can also be used as syntaxtic sugar to reference
> a property, breaking the clean design of verilog; [...]
>
> (seen onhttp://www.veripool.com/verilog-mode_news.html)

thanks jonathan and marcus...
seem that i need to read a lot of stuff..

regards,
hairo