This is a discussion on when using generic - vhdl ; Mike Treseler wrote: > Andy wrote: >> Thanks for the explanation. The syntax is confusing that the generic >> map applies to testbench (the object that the configuration >> configures), and not to the configuration itself (something inside >> testbench). ...
Mike Treseler wrote:
> Andy wrote:
>> Thanks for the explanation. The syntax is confusing that the generic
>> map applies to testbench (the object that the configuration
>> configures), and not to the configuration itself (something inside
>> testbench). Now I understand.
> I'm not sure I do. Looks to me like
> the base testbench entity is named tc
> its architecture is testcase_arch
> which instances another entity named testbench
> which gets the 100 ms value,
> if the library unit tc_testcase_cfg
> is run instead of tc.
Yes indeed. To run the simulation, the toplevel configuration
tc_testcase_cfg should be elaborated, not the entity tc.
Below is the complete picture. It is two-layered: a single testbench with
all the tedious stuff, such as all the plumbing connecting busfunctional
models to the DUV (device under verification).
And then there are lots of testcases, each instantiating the testbench and
optionally configuring the testbench by setting its generics in the
toplevel (testcase) configuration(s). Each testcase runs a specific
scenario, verifying a bunch of requirements of the DUV.
To make it even more complicated (well, in fact: easier): multiple
configurations of a single testcase may exist. That way, a scenario can be
run using for example an alternative RAM model connected to your DUV in the
testbench. You just supply a different generic to the testbench via the
alternative toplevel configuration.
The main goal of all this is to avoid duplication of code. The testcases
only contain the scenario specific stuff while the testbench contains the
stuff that is needed by each testcase. Without this, maintenance would be
****yzed into library tb_lib:
PACKAGE testbench_pkg IS
-- Signal declarations, used in the testbench, made visible in
-- the testcase
-- One of those is 'simulate', which, when set false, will stop all
-- clock generators and with that end the simulation
SIGNAL simulate : boolean := true;
-- Component declaration of the testbench, without generics, so
-- the ones without a default must be set in the configuration of
-- the testcase.
COMPONENT testbench IS
END COMPONENT testbench;
END PACKAGE testbench_pkg IS;
ENTITY testbench IS
timebomb : delay_length; -- No default value, so user must supply one
-- more generics for configuring the testbench
END ENTITY testbench;
USE work.testbench_pkg.ALL; -- Make signals from package available
ARCHITECTURE tb_arch IS
-- Private signal declarations that will not be visible in
-- the testcase
-- Instantiation of the DUV and verification components.
-- All plumbing to connect the components, clock generators,
-- reset generators, standard initialization sequences, etc
-- Timebomb and final simulation result
-- If the simulation does not stop on its own accord before the specified
-- maximum simulation time (via generic timebomb), the simulation is
-- aborted with an error (to prevent a run-away simulation blocking other
-- simulations in the queue).
sim_result: PROCESS IS
WAIT UNTIL NOT simulate FOR timebomb;
IF simulate THEN
REPORT "SIMULATION FAILED! Maximum simulation time expired"
-- Evaluation of error counters, score boards, etc resulting
-- in a final PASS/FAIL verdict.
END PROCESS sim_result;
END ARCHITECTURE tb_arch
CONFIGURATION testbench_cfg OF testbench IS
FOR myduv_i: myduv
USE ENTITY src_myduv_lib.duv(duv_arch);
-- More component bindings, for the verification components
-- such as bus functional models.
END CONFIGURATION testbench_cfg;
****yzed into library work:
ENTITY tc IS
END ENTITY tc;
USE tb_lib.testbench_pkg.ALL; -- Make signals from testbench available
ARCHITECTURE testcase_arch IS
-- Instantiation of the testbench
-- The actual scenario
do_sim: PROCESS IS
-- do reset and wait on end of reset
-- run the scenario
-- End of simulation
simulate <= false;
END PROCESS do_sim;
END ARCHITECTURE testcase_arch;
CONFIGURATION tc_testcase_cfg OF tc IS
FOR testbench_i: testbench
USE CONFIGURATION tb_lib.testbench_cfg
timebomb => 100 ms;
-- optionally more testbench settings
END CONFIGURATION tc_testcase_cfg;
To run the simulation (using ModelSim):
vsim -do 'run -a; quit' tc_testcase_cfg
e-mail addres: remove the not.