ISE timing constraint

Hi,

I need help for timing constraints in Xilinx virtex 4 Fx.

I have this design with two clocks on bufgmux and two components.

First clock : 50 Mhz
Second clock : 300 Mhz

Component A, need to work at 50Mhz
Component B, need to work at 300 Mhz

___________
| |
| |
|Component|
__________| A |
| | |
| |_________|
|
|\ |
CLK_50M ---| \ |
| \_________|
| / |
CLK_300M---| / |
|/ |
| ___________
| | |
|________| |
|Component|
| B |
|_________|

When I define both clock timing constraints on ucf file, ISE apply 300
Mhz for component A and B.
But the component A doesn't work at 300 Mhz and I don't whant that the
component A work at this frequency.

How i do for put the good frequency on each component whithout use two
bufg instead one bufgmux? (specific timing constraint)

Regards,

Yannick

Yannick wrote:
> Hi,
>
> I need help for timing constraints in Xilinx virtex 4 Fx.
>
> I have this design with two clocks on bufgmux and two components.
>
> First clock : 50 Mhz
> Second clock : 300 Mhz
>
> Component A, need to work at 50Mhz
> Component B, need to work at 300 Mhz
>
> ___________
> | |
> | |
> |Component|
> __________| A |
> | | |
> | |_________|
> |
> |\ |
> CLK_50M ---| \ |
> | \_________|
> | / |
> CLK_300M---| / |
> |/ |
> | ___________
> | | |
> |________| |
> |Component|
> | B |
> |_________|
>
> When I define both clock timing constraints on ucf file, ISE apply 300
> Mhz for component A and B.
> But the component A doesn't work at 300 Mhz and I don't whant that the
> component A work at this frequency.
>
> How i do for put the good frequency on each component whithout use two
> bufg instead one bufgmux? (specific timing constraint)
>
> Regards,
>
> Yannick


Yannick,

1) You're posting on the wrong newsgroup. Next time try comp.arch.fpga .
2) You need to RTFM. Specifically, the contraints guide.
3) In the UCF do this:-

INST "component_a_name*" TNM="component_a_bits";
TIMESPEC TS1 = FROM : component_a_bits : TO : component_a_bits : 50ns;

INST "component_b_name*" TNM="component_b_bits";
TIMESPEC TS2 = FROM : component_b_bits : TO : component_b_bits : 50ns;

HTH, Syms.

I meant :-
TIMESPEC TS2 = FROM : component_b_bits : TO : component_b_bits : 3.3ns;