Re: Quartus II infered latchesThis is a discussion on Re: Quartus II infered latches within the vhdl forums in Programming Languages category; On Aug 12, 7:49 am, jacko <jackokr...@gmail.com> wrote: > On 11 Aug, 18:16, Mike Treseler <mtrese...@gmail.com> wrote: > > I'm not complaining about the packing, it does a fine job. With > further testing and wrapping the carry in CARRY primitives, it has > proved that 29 of 32 CARRY_SUM primitives were ignored, and the size > went up about 20LEs and the speed dropped to 13MHz. Wierd! > > The chain is definatly detected. I was just wondering why there is > less inputs allowed on a chained LE. A replacement of input or output > by fast chain ... | ||||||||
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08-12-2008, 11:08 AM
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 Re: Quartus II infered latches On Aug 12, 7:49 am, jacko <jackokr...@gmail.com> wrote: > On 11 Aug, 18:16, Mike Treseler <mtrese...@gmail.com> wrote: > > I'm not complaining about the packing, it does a fine job. With > further testing and wrapping the carry in CARRY primitives, it has > proved that 29 of 32 CARRY_SUM primitives were ignored, and the size > went up about 20LEs and the speed dropped to 13MHz. Wierd! > > The chain is definatly detected. I was just wondering why there is > less inputs allowed on a chained LE. A replacement of input or output > by fast chain signal is understandable, but I don't get the 3 input > limit (one of them being a chain itself). The Altera devices I have used (ACEX 1K) are limited to 3 inputs when used in adders because they split the LUT into one 3-LUT for the sum and another 3-LUT for the carry. This could either be because they want to save some of the area used by the carry chain, or because the carry chain is patented. I expect it is the latter. Rick  |
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