Mixed clocked/combinatorial coding styles

rickman wrote:

> in the logic elements. Loading the FFs directly from the
> configuration bitstream would require muxes on the D input and the
> clock input. This would be a lot of extra logic in the chip for no
> purpose since the GSR signal will set or reset every FF in the design
> during configuration. You can then choose to use the GSR signal after
> configuration for your own purposes or not.

But for example in V5 you can set different init value for the FF
compared to the set/reset value that can be connected to the GSR signal
in functional mode. The real implementation might be that first the
init0/init1 attributes are set from the configuration to the SR
settings, after that internally GSR is asserted and after that the real
srhigh/srlow attributes are set up.

One again this is from the V5 manual:
"The initial state after configuration or global initial state is
defined by separate INIT0 and INIT1 attributes. By default, setting the
SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1.
Virtex-5 devices can set INIT0 and INIT1 independent of SRHIGH and
SRLOW."

But without the design spec for V5 we can just guess. My understanding
is that the high level logical schematic of a logical element (LUT+FF
etc) is quite different compared to the real transistor level
implementation. Also the FPGAs contain hidden undocumented features all
over the place, for certain customers those features can even be enabled
with special tool patches. So there are many things inside the chip
that are just not documented.


--Kim

On Aug 28, 1:52 am, Kim Enkovaara <kim.enkova...@iki.fi> wrote:
> rickman wrote:
> > in the logic elements. Loading the FFs directly from the
> > configuration bitstream would require muxes on the D input and the
> > clock input. This would be a lot of extra logic in the chip for no
> > purpose since the GSR signal will set or reset every FF in the design
> > during configuration. You can then choose to use the GSR signal after
> > configuration for your own purposes or not.
>
> But for example in V5 you can set different init value for the FF
> compared to the set/reset value that can be connected to the GSR signal
> in functional mode. The real implementation might be that first the
> init0/init1 attributes are set from the configuration to the SR
> settings, after that internally GSR is asserted and after that the real
> srhigh/srlow attributes are set up.
>
> One again this is from the V5 manual:
> "The initial state after configuration or global initial state is
> defined by separate INIT0 and INIT1 attributes. By default, setting the
> SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1.
> Virtex-5 devices can set INIT0 and INIT1 independent of SRHIGH and
> SRLOW."
>
> But without the design spec for V5 we can just guess. My understanding
> is that the high level logical schematic of a logical element (LUT+FF
> etc) is quite different compared to the real transistor level
> implementation. Also the FPGAs contain hidden undocumented features all
> over the place, for certain customers those features can even be enabled
> with special tool patches. So there are many things inside the chip
> that are just not documented.

From the use of SRLOW and SRHIGH I suspect this is not even addressing
the FF state. SR likely refers to the shift register that you get
when using the LUT memory as logic. The LUT memory *can* be set by
the configuration bit stream, but in none of the logic families I have
seen can it be controlled by the GSR signal. Did you find any mention
of what SRLOW, SRHIGH, INIT0 and INIT1 control?

Rick

rickman wrote:
> From the use of SRLOW and SRHIGH I suspect this is not even addressing
> the FF state. SR likely refers to the shift register that you get
> when using the LUT memory as logic. The LUT memory *can* be set by

Maybe you should even open the V5 user guide. SR* controls the set/reset
polarity. All four parameters were FF related configuration parameters.

> seen can it be controlled by the GSR signal. Did you find any mention
> of what SRLOW, SRHIGH, INIT0 and INIT1 control?

Yes, you can also if you open UG190.

--Kim